verilog-transceiver

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####################
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# Clocks
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####################
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create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
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set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports clk]
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####################
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# I/O constraints
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####################
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# bank 0/13/33 LVCMOS33
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# bank 34/35 Vadj
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set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports en]
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set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS18} [get_ports arstn]
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set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports data]
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set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports q]
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