verilog-transceiver
README.md
Usage
Dependencies
hdlmake
, make
, cocotb
, pytest
, vivado
, modelsim
, python
, chocolatey
, winget
Installation
Download python and git:
Clone repository:
git clone --recurse-submodules https://github.com/RDSik/verilog-transceiver.gitcd verilog-transceiver
Download packages:
pip install sixpip install hdlmakepip install cocotbpip install pytest
Download make (add to PATH system variable the Make bin folder: C:\Program Files (x86)\GnuWin32\bin):
winget install GnuWin32.make
Build project
Build trasceiver:
cd synhdlmakemake
Build only vivado project:
cd synhdlmakemake project
Simulation
Modelsim simulation
Using hdlmake:
cd sim/modelsimhdlmakemake
Using cocotb (with 64 bit Python use 64 bit Modelsim):
py -m venv myenv.\myenv\Scripts\activate.ps1cd .\sim\cocotb\modelsimpy -m pytest test.pydeactivate
Icarus simulation using cocotb:
py -m venv myenv.\myenv\Scripts\activate.ps1cd .\sim\cocotb\icaruspy -m pytest test.pygtkwave .\sim_build_transceiver\transceiver_top.vcddeactivate
Описание
Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit
Языки
Verilog
- Stata
- Tcl
- MATLAB
- SystemVerilog
- Python