verilog-transceiver

0

Описание

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

Языки

  • Verilog71,4%
  • Python19,3%
  • Stata7,9%
  • MATLAB0,8%
  • Tcl0,6%
2 года назад
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README.md

My Image

Usage

Dependencies

hdlmake
,
make
,
cocotb
,
pytest
,
vivado
,
modelsim
,
python
,
chocolatey
,
winget

Installation

Download python and git:

Clone repository:

Download packages:

Download make (add to PATH system variable the Make bin folder: C:\Program Files (x86)\GnuWin32\bin):

Build project

Build trasceiver:

Build only vivado project:

Simulation

Modelsim simulation

Using hdlmake:

Using cocotb (with 64 bit Python use 64 bit Modelsim):

Icarus simulation using cocotb: