verilog-transceiver
11 строк · 189.0 Байт
1open_project transceiver.xpr
2
3read_ip ../platform/xilinx/clk_wiz/clk_wiz.xci
4generate_target all [get_files *clk_wiz.xci]
5
6read_mem sin_val.dat
7
8read_mem neg_sin_val.dat
9
10close_project
11exit