forth-cpu

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-------------------------------------------------------------------------------
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--| @file tb.vhd
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--| @brief Main test bench.
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--|
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--| @author         Richard James Howe.
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--| @copyright      Copyright 2013-2019 Richard James Howe.
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--| @license        MIT
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--| @email          howe.r.j.89@gmail.com
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--|
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--| This test bench does quite a lot. It is not like normal VHDL test benches
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--| in the fact that it uses configurable variables that it reads in from a
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--| file, which it does in an awkward but usable fashion. It also has a
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--| partially working way of connecting a simulated UART to STDIN/STDOUT, which
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--| is a work in progress.
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--|
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--| It also tests multiple modules.
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--|
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-------------------------------------------------------------------------------
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library ieee,work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use std.textio.all;
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use work.util.all;
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use work.core_pkg.all;
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use work.vga_pkg.all;
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entity tb is
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end tb;
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architecture testing of tb is
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	constant g: common_generics := (
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		clock_frequency    => 100_000_000,
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		asynchronous_reset => true,
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		delay              => 0 ns);
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	constant number_of_interrupts:    positive := 8;
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	constant uart_baud:               positive := 115200;
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	constant configuration_file_name: string   := "tb.cfg";
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	constant uart_tx_time:            time     := (10*1000 ms) / 115200;
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	constant uart_default_input:      std_ulogic_vector(7 downto 0) := x"AA";
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	constant reset_period_us:         natural  := 1;
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	constant jitter_on:               boolean  := false;
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	constant clock_period:            time     := 1000 ms / g.clock_frequency;
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	constant tb_vga_on:               boolean  := false;
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	constant tb_uart_on:              boolean  := false;
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	constant tb_util_on:              boolean  := false;
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	-- Test bench configurable options --
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	type configurable_items is record
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		number_of_iterations: natural; -- 0 == loop forever
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		verbose:              boolean;
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		report_number:        natural;
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		interactive:          boolean;
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		input_wait_for:       time;
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	end record;
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	function set_configuration_items(ci: configuration_items) return configurable_items is
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		variable r: configurable_items;
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	begin
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		r.number_of_iterations := ci(0).value;
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		r.verbose              := ci(1).value > 0;
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		r.interactive          := ci(2).value > 0;
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		r.input_wait_for       := ci(3).value * 1 ms;
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		r.report_number        := ci(4).value;
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		return r;
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	end function;
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	constant configuration_default: configuration_items(0 to 4) := (
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		(name => "Cycles  ", value => 1000),
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		(name => "Verbose ", value => 1),
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		(name => "Interact", value => 0),
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		(name => "InWaitMs", value => 8),
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		(name => "LogFor  ", value => 256));
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	-- Test bench configurable options --
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	signal stop:  boolean := false;
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	signal dbgi:  cpu_debug_interface;
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	signal clk:          std_ulogic := '0';
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	signal rst:          std_ulogic := '0';
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	-- Basic I/O
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	signal btnu:  std_ulogic := '0';  -- button up
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	signal btnd:  std_ulogic := '0';  -- button down
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	signal btnc:  std_ulogic := '0';  -- button centre
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	signal btnl:  std_ulogic := '0';  -- button left
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	signal btnr:  std_ulogic := '0';  -- button right
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	signal sw:    std_ulogic_vector(7 downto 0) := (others => '0'); -- switches
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	signal an:    std_ulogic_vector(3 downto 0) := (others => '0'); -- anodes   8 segment display
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	signal ka:    std_ulogic_vector(7 downto 0) := (others => '0'); -- kathodes 8 segment display
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	signal ld:    std_ulogic_vector(7 downto 0) := (others => '0'); -- leds
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	-- VGA
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	signal o_vga: vga_physical_interface;
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	signal hsync_gone_high: boolean := false;
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	signal vsync_gone_high: boolean := false;
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	-- HID
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	signal ps2_keyboard_data: std_ulogic := '0';
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	signal ps2_keyboard_clk:  std_ulogic := '0';
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	-- UART
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	signal rx:                 std_ulogic := '0';
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	signal tx:                 std_ulogic := '0';
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	signal dout_ack, dout_stb: std_ulogic := '0';
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	signal din_ack, din_stb:   std_ulogic := '0';
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	signal dout:               std_ulogic_vector(7 downto 0) := (others => '0');
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	signal din:                std_ulogic_vector(7 downto 0) := (others => '0');
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	-- Wave form generator
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	signal gen_dout:     std_ulogic_vector(15 downto 0) := (others => '0');
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	shared variable cfg: configurable_items := set_configuration_items(configuration_default);
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	signal configured: boolean := false;
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	signal ram_cs:     std_ulogic := 'X';
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	signal mem_oe:     std_ulogic := 'X'; -- negative logic
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	signal mem_wr:     std_ulogic := 'X'; -- negative logic
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	signal mem_adv:    std_ulogic := 'X'; -- negative logic
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	signal mem_wait:   std_ulogic := 'X'; -- positive!
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	signal flash_cs:   std_ulogic := 'X';
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	signal flash_rp:   std_ulogic := 'X';
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	signal mem_addr:   std_ulogic_vector(26 downto 1) := (others => 'X');
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	signal mem_data:   std_logic_vector(15 downto 0)  := (others => 'X');
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begin
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---- Units under test ----------------------------------------------------------
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	mem_data <= (others => '0') when mem_oe = '1' else (others => 'Z');
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	uut: entity work.top
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	generic map(
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		g               => g,
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		reset_period_us => reset_period_us,
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		uart_baud  => uart_baud)
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	port map(
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		debug       => dbgi,
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		clk         => clk,
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		-- rst      => rst,
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		btnu        => btnu,
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		btnd        => btnd,
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		btnc        => btnc,
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		btnl        => btnl,
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		btnr        => btnr,
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		sw          => sw,
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		an          => an,
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		ka          => ka,
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		ld          => ld,
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		rx          => rx,
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		tx          => tx,
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		o_vga       => o_vga,
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		ps2_keyboard_data => ps2_keyboard_data,
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		ps2_keyboard_clk  => ps2_keyboard_clk,
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		ram_cs    =>  ram_cs,
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		mem_oe    =>  mem_oe,
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		mem_wr    =>  mem_wr,
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		mem_adv   =>  mem_adv,
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		mem_wait  =>  mem_wait,
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		flash_cs  =>  flash_cs,
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		flash_rp  =>  flash_rp,
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		mem_addr  =>  mem_addr,
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		mem_data  =>  mem_data);
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	-- NB. It would be nice to configure these as off/on, as well as
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	-- controlling how long they run for from here.
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	util_g: if tb_util_on generate uut_util: work.util.util_tb     generic map(g => g); end generate;
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	vga_g:  if tb_vga_on  generate uut_vga:  work.vga_pkg.vt100_tb generic map(g => g); end generate;
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	uart_g: if tb_uart_on generate uut_uart: work.uart_pkg.uart_tb generic map(g => g); end generate;
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	uart_0_blk: block
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		signal uart_clock_rx_we, uart_clock_tx_we, uart_control_we: std_ulogic := '0';
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		signal uart_reg: std_ulogic_vector(15 downto 0);
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	begin
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		uart_0: work.uart_pkg.uart_core
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			generic map (g => g, baud => uart_baud)
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			port map (
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				clk   => clk,
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				rst   => rst,
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				tx_di => din,
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				tx_we => din_stb,
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				tx_ok => din_ack,
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				tx    => rx,
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				rx    => tx,
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				rx_ok => open,
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				rx_nd => dout_stb,
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				rx_do => dout,
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				rx_re => dout_ack,
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				reg             => uart_reg,
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				clock_reg_tx_we => uart_clock_tx_we,
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				clock_reg_rx_we => uart_clock_rx_we,
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				control_reg_we  => uart_control_we);
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	end block;
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------ Simulation only processes ----------------------------------------------
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	clk_process: process
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		variable seed1, seed2 : positive;
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		variable r : real;
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		variable jit_high, jit_low: time  := 0 ns;
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	begin
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		while not stop loop
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			if jitter_on then
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				uniform(seed1, seed2, r);
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				jit_high := r * g.delay;
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				uniform(seed1, seed2, r);
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				jit_low := r * g.delay;
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				uniform(seed1, seed2, r);
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				if r < 0.5 then jit_high := -jit_high; end if;
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				uniform(seed1, seed2, r);
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				if r < 0.5 then jit_low := -jit_low; end if;
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			else
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				jit_high := 0 ns;
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				jit_low  := 0 ns;
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			end if;
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			clk <= '1';
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			wait for (clock_period / 2) + jit_high;
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			clk <= '0';
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			wait for (clock_period / 2) + jit_low;
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		end loop;
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		report "clk_process end";
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		wait;
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	end process;
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	output_process: process
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		variable oline: line;
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		variable c: character;
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		variable have_char: boolean := true;
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	begin
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		wait until configured;
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		if not cfg.interactive then
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			report "Output turned off";
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			report "output_process end";
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			wait;
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		end if;
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		report "Writing to STDOUT";
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		while not stop loop
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			wait until (dout_stb = '1' or stop);
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			if not stop then
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				c := character'val(to_integer(unsigned(dout)));
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				write(oline, c);
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				have_char := true;
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				if dout = x"0d" then
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					writeline(output, oline);
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					have_char := false;
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				end if;
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				wait for clock_period;
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				dout_ack <= '1';
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				wait for clock_period;
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				dout_ack <= '0';
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			end if;
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		end loop;
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		if have_char then
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			writeline(output, oline);
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		end if;
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		report "output_process end";
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		wait;
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	end process;
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	-- The Input and Output mechanism that allows the tester to
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	-- interact with the running simulation needs more work, it is buggy
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	-- and experimental, but demonstrates the principle - that a VHDL
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	-- test bench can be interacted with at run time.
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	input_process: process
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		variable c: character := ' ';
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		variable iline: line;
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		-- variable oline: line;
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		variable good: boolean := true;
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		variable eoi:  boolean := false;
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	begin
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		din_stb <= '0';
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		din     <= x"00";
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		wait until configured;
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		if not cfg.interactive then
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			din_stb <= '1';
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			din     <= uart_default_input;
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			report "input process non-interactive";
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			report "input_process end";
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			wait;
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		end if;
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		report "Waiting for " & time'image(cfg.input_wait_for) & " (before reading from STDIN)";
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		wait for cfg.input_wait_for;
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		report "Reading from STDIN (Hit EOF/CTRL-D/CTRL-Z After entering a line)";
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		while (not endfile(input)) and not stop and eoi = false loop
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			report "readline...";
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			readline(input, iline);
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			good := true;
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			while good and not stop loop
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				read(iline, c, good);
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				if good then
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					report "" & c;
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				else
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					report "EOL/EOI";
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					c   := LF;
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					eoi := true;
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				end if;
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				din <= std_ulogic_vector(to_unsigned(character'pos(c), din'length));
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				din_stb <= '1';
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				wait for clock_period;
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				din_stb <= '0';
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				wait for 100 us;
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			end loop;
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		end loop;
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		report "input_process end";
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		wait;
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	end process;
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	hsync_gone_high <= true when o_vga.hsync = '1' else hsync_gone_high;
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	vsync_gone_high <= true when o_vga.vsync = '1' else vsync_gone_high;
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	-- I/O settings go here.
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	stimulus_process: process
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		variable w: line;
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		variable count: integer := 0;
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		function stringify(slv: std_ulogic_vector) return string is
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		begin
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			return integer'image(to_integer(unsigned(slv)));
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		end stringify;
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		procedure element(l: inout line; we: boolean; name: string; slv: std_ulogic_vector) is
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		begin
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			if we then
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				write(l, name & "(" & stringify(slv) & ") ");
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			end if;
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		end procedure;
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		procedure element(l: inout line; name: string; slv: std_ulogic_vector) is
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		begin
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			element(l, true, name, slv);
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		end procedure;
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		function reportln(debug: cpu_debug_interface; cycles: integer) return line is
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			variable l: line;
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		begin
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			write(l, integer'image(cycles) & ": ");
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			element(l, "pc",    debug.pc);
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			element(l, "insn",  debug.insn);
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			element(l, "daddr", debug.daddr);
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			element(l, "dout",  debug.dout);
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			return l;
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		end function;
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		variable configuration_values: configuration_items(configuration_default'range) := configuration_default;
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	begin
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		-- write_configuration_tb(configuration_file_name, configuration_default);
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		read_configuration_tb(configuration_file_name, configuration_values);
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		cfg := set_configuration_items(configuration_values);
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		configured <= true;
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		rst  <= '1';
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		wait for clock_period * 2;
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		rst  <= '0';
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		if cfg.number_of_iterations = 0 then
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			report "RUNNING FOREVER: number of iterations is zero" severity warning;
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			report "stimulus_process end";
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			wait;
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		end if;
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		for i in 0 to cfg.number_of_iterations loop
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			if cfg.verbose then
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				if count < cfg.report_number then
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					w := reportln(dbgi, count);
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					writeline(OUTPUT, w);
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					count := count + 1;
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				elsif count < cfg.report_number + 1 then
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					report "Simulation continuing: Reporting turned off";
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					count := count + 1;
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				end if;
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			end if;
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			wait for clock_period * 1;
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		end loop;
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		-- These HSYNC and VSYNC asserts are included under the assumption
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		-- that the image running on the H2 CPU will initiate the VGA, if
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		-- it does not (perhaps because it is running it's own initialization
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		-- routines), then the HSYNC or VSYNC will never go high - so this is
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		-- not necessarily an error.
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		--
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		-- It would be nice to test the other peripherals as
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		-- well, the CPU-ID should be written to the LED 7 Segment
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		-- displays, however we only get the cathode and anode
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		-- values out of the unit.
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		assert hsync_gone_high report "HSYNC not active - H2 failed to initialize VGA module";
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		assert vsync_gone_high report "VSYNC not active - H2 failed to initialize VGA module";
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		stop   <=  true;
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		report "stimulus_process end";
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		wait;
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	end process;
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end architecture;
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------ END ---------------------------------------------------------------------
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