forth-cpu
/
ram.vhd
125 строк · 4.7 Кб
1-------------------------------------------------------------------------------
2--| @file ram.vhd
3--| @brief Bus Interface to Nexys3 on board memory devices
4--| @author Richard James Howe
5--| @copyright Copyright 2017 Richard James Howe.
6--| @license MIT
7--| @email howe.r.j.89@gmail.com
8--|
9--| This component is for interfacing with the two memory devices available
10--| on the Nexys3 board.
11--|
12--| The devices are:
13--| - PC28F128P33BF60 (Non-Volatile Flash with a CSI Interface)
14--| - MT45W1MW16BDGB (SRAM)
15--|
16--| They both share the same data, address lines, output enable, and write
17--| enable signals. They are selected with a Chip Select (ram_cs = SRAM,
18--| flash_cs = Flash device). The Flash has an addition reset line (flash_rp).
19--|
20--| This interface is very simple, it does not bother with timing and
21--| only has minimal logic and state, it is up to the consumer of this
22--| module to implement the bus timing - which in this case is a Soft CPU
23--| Core.
24--|
25--| Many improvements could be made, we could do a lot more in the hardware,
26--| even going as far as to implement most of the Common Flash Interface (but
27--| that would be better placed in a controlling module), but it is not
28--| necessary. We will Keep It Simple.
29--|
30-------------------------------------------------------------------------------
31library ieee, work;
32use ieee.std_logic_1164.all;
33use work.util.common_generics;
34
35entity ram_interface is
36generic (g: common_generics);
37port(
38clk: in std_ulogic;
39rst: in std_ulogic;
40
41mem_addr_16_1: in std_ulogic_vector(16 downto 2);
42mem_addr_16_1_we: in std_ulogic;
43mem_addr_26_17: in std_ulogic_vector(26 downto 17);
44mem_addr_26_17_we: in std_ulogic;
45mem_control_i: in std_ulogic_vector(5 downto 0);
46mem_control_we: in std_ulogic;
47mem_data_i: in std_ulogic_vector(15 downto 0);
48mem_data_i_we: in std_ulogic;
49
50mem_data_o: out std_ulogic_vector(15 downto 0);
51
52ram_cs: out std_ulogic := '1';
53
54mem_oe: out std_ulogic := '0'; -- negative logic
55mem_wr: out std_ulogic := '0'; -- negative logic
56mem_adv: out std_ulogic := '0'; -- negative logic
57mem_wait: out std_ulogic := '0'; -- positive!
58
59flash_cs: out std_ulogic := '0';
60flash_rp: out std_ulogic := '1';
61mem_addr: out std_ulogic_vector(26 downto 1) := (others => '0');
62mem_data: inout std_logic_vector(15 downto 0) := (others => 'Z'));
63end entity;
64
65architecture rtl of ram_interface is
66signal mem_data_buf_i: std_ulogic_vector(mem_data_i'range) := (others => '0');
67signal mem_control_o: std_ulogic_vector(mem_control_i'range) := (others => '0');
68signal mem_we: std_ulogic := '0';
69signal mem_oe_internal: std_ulogic := '0';
70signal mem_addr_low: std_ulogic_vector(mem_addr_16_1'range) := (others => '0');
71signal mem_addr_high: std_ulogic_vector(mem_addr_26_17'range) := (others => '0');
72begin
73mem_addr <= '0' & mem_addr_high & mem_addr_low;
74
75mem_addr_16_1_reg: entity work.reg
76generic map(g => g, N => mem_addr_16_1'length)
77port map(
78clk => clk,
79rst => rst,
80we => mem_addr_16_1_we,
81di => mem_addr_16_1,
82do => mem_addr_low);
83
84mem_addr_26_17_reg: entity work.reg
85generic map(g => g, N => mem_addr_26_17'length)
86port map(
87clk => clk,
88rst => rst,
89we => mem_addr_26_17_we,
90di => mem_addr_26_17,
91do => mem_addr_high);
92
93mem_control_reg: entity work.reg
94generic map(g => g, N => mem_control_i'length)
95port map(
96clk => clk,
97rst => rst,
98we => mem_control_we,
99di => mem_control_i,
100do => mem_control_o);
101
102mem_data_i_reg: entity work.reg
103generic map(g => g, N => mem_data_i'length)
104port map(
105clk => clk,
106rst => rst,
107we => mem_data_i_we,
108di => mem_data_i,
109do => mem_data_buf_i);
110
111flash_cs <= '0' when mem_control_o(5 downto 4) /= "00" and mem_control_o(0) = '1' else '1' after g.delay;
112ram_cs <= '0' when mem_control_o(5 downto 4) /= "00" and mem_control_o(1) = '1' else '1' after g.delay;
113mem_wait <= mem_control_o(2);
114flash_rp <= '0' when mem_control_o(3) = '1' else '1' after g.delay;
115mem_adv <= '0' when mem_oe_internal = '1' or mem_we = '1' else '1' after g.delay;
116mem_oe_internal <= '1' when mem_control_o(5 downto 4) = "01" else '0' after g.delay;
117mem_we <= '1' when mem_control_o(5 downto 4) = "10" else '0' after g.delay;
118
119mem_oe <= not mem_oe_internal after g.delay;
120mem_wr <= not mem_we after g.delay;
121
122mem_data_o <= std_ulogic_vector(mem_data) when mem_oe_internal = '1' else (others => '0') after g.delay;
123mem_data <= std_logic_vector(mem_data_buf_i) when mem_we = '1' else (others => 'Z') after g.delay;
124
125end architecture;
126