forth-cpu

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#
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# Makefile to simulate and synthesize VHDL designs
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#
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# @Author      Marc Eberhard/Richard Howe
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# @Copyright   Copyright 2013 Marc Eberhard, 2016,2020 Richard Howe
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# @License     LGPL
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#
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# This makefile can build the toolchain, simulators, and the bit
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# file for the FPGA. Type "make help" at the command line for a
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# list of options
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#
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NETLIST=top
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CFLAGS=-Wall -Wextra -O2 -g -pedantic
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CC=gcc
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TIME=
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#TIME=time -p 
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OS_FLAGS =
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# From: https://stackoverflow.com/questions/714100/os-detecting-makefile
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ifeq ($(OS),Windows_NT)
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GUI_LDFLAGS = -lfreeglut -lopengl32 -lm 
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DF=
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EXE=.exe
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.PHONY: h2 gui text block
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h2:     h2.exe
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gui:    gui.exe
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text:   text.exe
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block:  block.exe
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else # assume unixen
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GUI_LDFLAGS = -lglut -lGL -lm 
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DF=./
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EXE=
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endif
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.PHONY: simulation viewer synthesis bitfile upload clean run gui-run 
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## Remember to update the synthesis section as well
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SOURCES = \
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	util.vhd \
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	timer.vhd \
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	uart.vhd \
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	kbd.vhd \
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	vga.vhd \
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	h2.vhd \
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	ram.vhd \
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	core.vhd
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OBJECTS = ${SOURCES:.vhd=.o}
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all:
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	@echo ""
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	@echo "Simulation:"
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	@echo ""
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	@echo "make simulation     - simulate VHDL design"
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	@echo "make viewer         - start waveform viewer for simulation results"
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	@echo "make documentation  - build the PDF and HTML documentation"
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	@echo "make h2${EXE}             - build C based CLI emulator for the VHDL SoC"
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	@echo "make gui${EXE}            - build C based GUI emulator for the Nexys3 board"
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	@echo "make run            - run the C CLI emulator on h2.fth"
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	@echo "make gui-run        - run the GUI emulator on ${EFORTH}"
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	@echo ""
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	@echo "Synthesis:"
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	@echo ""
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	@echo "make synthesis      - synthesize design"
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	@echo "make implementation - implement design"
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	@echo "make bitfile        - generate bitfile"
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	@echo ""
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	@echo "Upload:"
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	@echo ""
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	@echo "make upload         - upload design to FPGA"
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	@echo ""
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	@echo "Cleanup:"
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	@echo ""
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	@echo "make clean          - delete temporary files and cleanup directory"
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	@echo ""
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## Documentation ===========================================================
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documentation: readme.pdf readme.htm
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%.pdf: %.md
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	pandoc -V geometry:margin=0.5in --toc $< -o $@
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%.htm: %.md
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	pandoc --toc --self-contained $^ -o $@
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## Assembler, Virtual Machine and UART communications ======================
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EFORTH=h2.hex
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h2${EXE}: h2.c h2.h
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	${CC} ${CFLAGS} -std=c99 $< -o $@
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embed${EXE}: embed.c
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	${CC} ${CFLAGS} -std=c99 $< -o $@
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${EFORTH}: embed${EXE} embed.blk embed.fth
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	${DF}embed${EXE} embed.blk $@ embed.fth
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block${EXE}: block.c
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	${CC} ${CFLAGS} -std=c99 $< -o $@
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nvram.blk: nvram.txt block${EXE} 
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	${DF}block${EXE} < nvram.txt >  $@
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run: h2${EXE} ${EFORTH} text.hex nvram.blk
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	${DF}h2 -H -r ${EFORTH}
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h2nomain.o: h2.c h2.h
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	${CC} ${CFLAGS} -std=c99 -DNO_MAIN  $< -c -o $@
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gui.o: gui.c h2.h
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	${CC} ${CFLAGS} -std=gnu99  $< -c -o $@
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gui${EXE}: h2nomain.o gui.o
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	${CC} ${CFLAGS} $^ ${GUI_LDFLAGS} -o $@
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gui-run: gui${EXE} ${EFORTH} nvram.blk text.hex
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	${DF}$< ${EFORTH}
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text${EXE}: text.c
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	${CC} ${CFLAGS} -std=c99 $< -o $@
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text.hex: text${EXE}
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	${DF}$< -g > $@
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## Simulation ==============================================================
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%.o: %.vhd
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	ghdl -a -g $<
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ram.o: util.o
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kbd.o: util.o kbd.vhd
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vga.o: util.o vga.vhd text.hex font.bin
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core.o: util.o h2.o core.vhd ${EFORTH}
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uart.o: util.o uart.vhd
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timer.o: util.o
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top.o: util.o timer.o core.o uart.o vga.o kbd.o ram.o top.vhd  
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tb.o: top.o util.o tb.vhd 
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tb: ${OBJECTS} tb.o
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	ghdl -e tb
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# max stack alloc needed for GHDL >0.35
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# ghdl -r $< --wave=$<.ghw --max-stack-alloc=16384 --unbuffered --ieee-asserts=disable 
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%.ghw: % %.cfg
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	ghdl -r $< --wave=$<.ghw --max-stack-alloc=16384 --ieee-asserts=disable --unbuffered
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simulation: tb.ghw h2${EXE}
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## Simulation ==============================================================
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ifeq ($(OS),Windows_NT)
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viewer: simulation signals.tcl
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	gtkwave -S signals.tcl -f tb.ghw 
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else
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viewer: simulation signals.tcl
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	gtkwave -S signals.tcl -f tb.ghw &> /dev/null&
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endif
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USB?=/dev/ttyUSB0
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BAUD?=115200
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#BAUD?=9600
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talk:
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	picocom --omap delbs -e b -b ${BAUD} ${USB}
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bitfile: design.bit
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reports:
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	@[ -d reports    ]    || mkdir reports
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tmp:
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	@[ -d tmp        ]    || mkdir tmp
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tmp/_xmsgs:
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	@[ -d tmp/_xmsgs ]    || mkdir tmp/_xmsgs
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tmp/top.prj: tmp
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	@rm -f tmp/top.prj
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	@( \
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	    for f in $(SOURCES); do \
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	        echo "vhdl work \"$$f\""; \
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	    done; \
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	    echo "vhdl work \"top.vhd\"" \
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	) > tmp/top.prj
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tmp/top.lso: tmp
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	@echo "work" > tmp/top.lso
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tmp/top.xst: tmp tmp/_xmsgs tmp/top.lso tmp/top.lso
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	@( \
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	    echo "set -tmpdir \"tmp\""; \
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	    echo "set -xsthdpdir \"tmp\""; \
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	    echo "run"; \
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	    echo "-lso tmp/top.lso"; \
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	    echo "-ifn tmp/top.prj"; \
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	    echo "-ofn top"; \
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	    echo "-p xc6slx16-csg324-3"; \
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	    echo "-top top"; \
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	    echo "-opt_mode speed"; \
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	    echo "-opt_level 2" \
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	) > tmp/top.xst
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synthesis: ${EFORTH} text.hex reports tmp tmp/_xmsgs tmp/top.prj tmp/top.xst
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	@echo "Synthesis running..."
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	@${TIME} xst -intstyle silent -ifn tmp/top.xst -ofn reports/xst.log
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	@mv _xmsgs/* tmp/_xmsgs
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	@rmdir _xmsgs
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	@mv top_xst.xrpt tmp
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	@grep "ERROR\|WARNING" reports/xst.log | \
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	 grep -v "WARNING.*has a constant value.*This FF/Latch will be trimmed during the optimization process." | \
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	 cat
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	@grep ns reports/xst.log | grep 'Clock period'
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implementation: reports tmp
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	@echo "Implementation running..."
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	@[ -d tmp/xlnx_auto_0_xdb ] || mkdir tmp/xlnx_auto_0_xdb
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	@${TIME} ngdbuild -intstyle silent -quiet -dd tmp -uc top.ucf -p xc6slx16-csg324-3 top.ngc top.ngd
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	@mv top.bld reports/ngdbuild.log
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	@mv _xmsgs/* tmp/_xmsgs
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	@rmdir _xmsgs
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	@mv xlnx_auto_0_xdb/* tmp
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	@rmdir xlnx_auto_0_xdb
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	@mv top_ngdbuild.xrpt tmp
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	@${TIME} map -intstyle silent -detail -p xc6slx16-csg324-3 -pr b -c 100 -w -o top_map.ncd top.ngd top.pcf
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	@mv top_map.mrp reports/map.log
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	@mv _xmsgs/* tmp/_xmsgs
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	@rmdir _xmsgs
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	@mv top_usage.xml top_summary.xml top_map.map top_map.xrpt tmp
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	@${TIME} par -intstyle silent -w -ol std top_map.ncd top.ncd top.pcf
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	@mv top.par reports/par.log
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	@mv top_pad.txt reports/par_pad.txt
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	@mv _xmsgs/* tmp/_xmsgs
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	@rmdir _xmsgs
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	@mv par_usage_statistics.html top.ptwx top.pad top_pad.csv top.unroutes top.xpi top_par.xrpt tmp
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	@#trce -intstyle silent -v 3 -s 3 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf top.ucf
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	@#mv top.twr reports/trce.log
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	@#mv _xmsgs/* tmp/_xmsgs
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	@#rmdir _xmsgs
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	@#mv top.twx tmp
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	@#netgen -intstyle silent -ofmt vhdl -sim -w top.ngc top_xsim.vhd
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	@#netgen -intstyle silent -ofmt vhdl -sim -w -pcf top.pcf top.ncd top_tsim.vhd
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	@#mv _xmsgs/* tmp/_xmsgs
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	@#rmdir _xmsgs
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	@#mv top_xsim.nlf top_tsim.nlf tmp
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design.bit: reports tmp/_xmsgs
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	@echo "Generate bitfile running..."
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	@touch webtalk.log
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	@${TIME} bitgen -intstyle silent -w top.ncd
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	@mv top.bit design.bit
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	@mv top.bgn reports/bitgen.log
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	@mv _xmsgs/* tmp/_xmsgs
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	@rmdir _xmsgs
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	@sleep 5
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	@mv top.drc top_bitgen.xwbt top_usage.xml top_summary.xml webtalk.log tmp
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	@grep -i '\(warning\|clock period\)' reports/xst.log
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upload: 
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	djtgcfg prog -d Nexys3 -i 0 -f design.bit
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design: clean simulation synthesis implementation bitfile
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postsyn:
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	@netgen -w -ofmt vhdl -sim ${NETLIST}.ngc post_synthesis.vhd
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	@netgen -w -ofmt vhdl -sim ${NETLIST}.ngd post_translate.vhd
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	@netgen  -pcf ${NETLIST}.pcf -w -ofmt vhdl -sim ${NETLIST}.ncd post_map.vhd
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clean:
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	git clean -dffx
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