forth-cpu
/
h2.vhd
374 строки · 15.5 Кб
1-------------------------------------------------------------------------------
2--| @file h2.vhd
3--| @brief The H2 Processor: J1 processor translation and extension.
4--| Moved bit 12 to bit 4 to allow for more ALU instructions.
5--|
6--| @author Richard James Howe.
7--| @copyright Copyright 2017, 2019 Richard James Howe.
8--| @license MIT
9--| @email howe.r.j.89@gmail.com
10--|
11--| NB. It would be nice to be able to specify the CPU word length with a
12--| generic, so we could instantiate a 32-bit CPU if we wanted to.
13-------------------------------------------------------------------------------
14
15library ieee,work,std;
16use ieee.std_logic_1164.all;
17use ieee.numeric_std.all;
18
19package h2_pkg is
20subtype word is std_ulogic_vector(15 downto 0);
21subtype address is std_ulogic_vector(12 downto 0);
22
23constant hardware_cpu_id: word := X"0666";
24constant simulation_cpu_id: word := X"1984";
25
26component h2 is
27generic(
28asynchronous_reset: boolean := true; -- use asynchronous reset if true, synchronous if false
29delay: time := 0 ns; -- simulation only, gate delay
30
31cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction
32interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts
33start_address: natural := 0; -- Initial program counter value
34stack_size_log2: positive := 6; -- Log_2 of the Size of the stack
35use_interrupts: boolean := true -- Enable Interrupts in the H2 Core
36);
37port(
38clk: in std_ulogic;
39rst: in std_ulogic; -- active high reset, configurable async/sync
40stop: in std_ulogic; -- Assert high to halt the H2 core
41
42-- IO interface
43io_wr: out std_ulogic; -- Output Write Enable
44io_re: out std_ulogic; -- Input Read Enable
45io_din: in word; -- Data Input from register
46io_dout: out word; -- Data Output to register
47io_daddr: out word; -- Data Address for I/O action
48
49irq: in std_ulogic; -- Interrupt Request
50irq_addr: in std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request
51
52-- RAM interface, Dual port
53pc: out address; -- program counter
54insn: in word; -- instruction
55
56dwe: out std_ulogic; -- RAM data write enable
57dre: out std_ulogic; -- RAM data read enable
58din: in word; -- RAM data input
59dout: out word; -- RAM data output
60daddr: out address); -- RAM address
61end component;
62end;
63
64library ieee,work,std;
65use ieee.std_logic_1164.all;
66use ieee.numeric_std.all;
67use ieee.math_real.all; -- only needed for calculations relating to generics
68use work.h2_pkg.all;
69
70entity h2 is
71generic(
72asynchronous_reset: boolean := true; -- use asynchronous reset if true, synchronous if false
73delay: time := 0 ns; -- simulation only, gate delay
74
75cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction
76interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts
77start_address: natural := 0; -- Initial program counter value
78stack_size_log2: positive := 6; -- Log_2 of the Size of the stack
79use_interrupts: boolean := true); -- Enable Interrupts in the H2 Core
80port(
81clk: in std_ulogic;
82rst: in std_ulogic;
83
84-- IO interface
85stop: in std_ulogic; -- Assert high to halt the H2 core
86
87io_wr: out std_ulogic; -- Output Write Enable
88io_re: out std_ulogic; -- Input Read Enable
89io_din: in word; -- Data Input from register
90io_dout: out word; -- Data Output to register
91io_daddr: out word; -- Data Address for I/O action
92
93irq: in std_ulogic; -- Interrupt Request
94irq_addr: in std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request
95
96-- RAM interface, Dual port
97pc: out address; -- program counter
98insn: in word; -- instruction
99
100dwe: out std_ulogic; -- RAM data write enable
101dre: out std_ulogic; -- RAM data read enable
102din: in word; -- RAM data input
103dout: out word; -- RAM data output
104daddr: out address); -- RAM address
105end;
106
107architecture rtl of h2 is
108signal pc_c: address := std_ulogic_vector(to_unsigned(start_address, address'length));
109signal pc_n: address := (others => '0');
110signal pc_plus_one: address := (others => '0');
111
112constant stack_size: integer := 2 ** stack_size_log2;
113type stack_type is array (stack_size - 1 downto 0) of word;
114subtype depth is unsigned(stack_size_log2 - 1 downto 0);
115
116signal vstkp_c, vstkp_n: depth := (others => '0'); -- variable stack pointer
117signal vstk_ram: stack_type := (others => (others => '0')); -- variable stack
118signal dstk_we: std_ulogic := '0'; -- variable stack write enable
119signal dd: depth := (others => '0'); -- variable stack delta
120
121signal rstkp_c, rstkp_n: depth := (others => '0'); -- return stack pointer
122signal rstk_ram: stack_type := (others => (others => '0')); -- return stack
123signal rstk_we: std_ulogic := '0'; -- return stack write enable
124signal rd: depth := (others => '0'); -- return stack delta
125
126type instruction_info_type is record
127alu: std_ulogic;
128lit: std_ulogic;
129branch: std_ulogic;
130branch0: std_ulogic;
131call: std_ulogic;
132end record;
133
134signal is_instr: instruction_info_type := ('0', '0', '0', '0', '0');
135signal is_interrupt: std_ulogic := '0';
136signal is_ram_write: std_ulogic := '0';
137
138type compare_type is record
139more: std_ulogic; -- signed greater than; T > N?
140equal: std_ulogic; -- equality; N = T?
141umore: std_ulogic; -- unsigned greater than; T > N?
142zero: std_ulogic; -- zero test; T = 0?
143end record;
144
145signal compare: compare_type := ('0', '0', '0', '0');
146
147signal stop_c: std_ulogic := '1'; -- processor wait state register (current)
148signal stop_n: std_ulogic := '0'; -- processor wait state register (next)
149
150signal irq_en_c, irq_en_n: std_ulogic := '0'; -- interrupt enable
151signal irq_c, irq_n: std_ulogic := '0'; -- pending interrupt request
152signal irq_addr_c, irq_addr_n: std_ulogic_vector(irq_addr'range) := (others => '0'); -- address of pending interrupt request vector
153
154signal tos_c, tos_n: word := (others => '0'); -- top of stack
155signal nos: word := (others => '0'); -- next on stack
156signal rtos_c: word := (others => '0'); -- top of return stack
157signal rstk_data: word := (others => '0'); -- return stack input
158signal aluop: std_ulogic_vector(4 downto 0) := (others => '0'); -- ALU operation
159
160signal instruction: word := (others => '0'); -- processed 'insn'
161begin
162assert stack_size > 4 report "stack size too small: " & integer'image(stack_size) severity failure;
163-- assert dd /= "10" severity warning; -- valid, but odd (now used)
164
165is_instr.branch <= '1' when instruction(15 downto 13) = "000" else '0' after delay;
166is_instr.branch0 <= '1' when instruction(15 downto 13) = "001" else '0' after delay;
167is_instr.call <= '1' when instruction(15 downto 13) = "010" else '0' after delay;
168is_instr.alu <= '1' when instruction(15 downto 13) = "011" else '0' after delay;
169is_instr.lit <= '1' when instruction(15) = '1' else '0' after delay;
170is_ram_write <= '1' when is_instr.alu = '1' and instruction(5) = '1' else '0' after delay;
171compare.more <= '1' when signed(tos_c) > signed(nos) else '0' after delay;
172compare.umore <= '1' when unsigned(tos_c) > unsigned(nos) else '0' after delay;
173compare.equal <= '1' when tos_c = nos else '0' after delay;
174compare.zero <= '1' when unsigned(tos_c(15 downto 0)) = 0 else '0' after delay;
175nos <= vstk_ram(to_integer(vstkp_c)) after delay;
176rtos_c <= rstk_ram(to_integer(rstkp_c)) after delay;
177pc <= pc_n after delay;
178pc_plus_one <= std_ulogic_vector(unsigned(pc_c) + 1) after delay;
179dout <= nos after delay;
180daddr <= tos_c(13 downto 1) when is_ram_write = '1' else tos_n(13 downto 1) after delay;
181dwe <= '1' when is_ram_write = '1' and tos_c(15 downto 14) = "00" else '0' after delay;
182dre <= '1' when tos_n(15 downto 14) = "00" else '0' after delay;
183io_dout <= nos after delay;
184io_daddr <= tos_c after delay;
185io_wr <= '1' when is_ram_write = '1' and tos_c(15 downto 14) /= "00" else '0' after delay;
186is_interrupt <= '1' when irq_c = '1' and irq_en_c = '1' and use_interrupts else '0' after delay;
187irq_n <= irq after delay;
188irq_addr_n <= irq_addr after delay;
189stop_n <= stop after delay;
190dd(0) <= instruction(0) after delay;
191rd(0) <= instruction(2) after delay;
192dd(dd'high downto 1) <= (others => '1') when instruction(1) = '1' else (others => '0') after delay; -- sign extend
193rd(rd'high downto 1) <= (others => '1') when instruction(3) = '1' else (others => '0') after delay; -- sign extend
194dstk_we <= '1' when (is_instr.lit = '1' or (is_instr.alu = '1' and instruction(7) = '1')) else '0' after delay;
195
196next_state: process(clk, rst)
197procedure reset is
198begin
199pc_c <= std_ulogic_vector(to_unsigned(start_address, pc_c'length)) after delay;
200stop_c <= '1' after delay; -- start in stopped state
201vstkp_c <= (others => '0') after delay;
202rstkp_c <= (others => '0') after delay;
203tos_c <= (others => '0') after delay;
204irq_addr_c <= (others => '0') after delay;
205irq_en_c <= '0' after delay;
206irq_c <= '0' after delay;
207end reset;
208begin
209if rst = '1' and asynchronous_reset then
210reset;
211elsif rising_edge(clk) then
212if rst = '1' and not asynchronous_reset then
213reset;
214else
215assert stop_c = '0' or (stop_c = '1' and is_instr.branch = '1') severity failure;
216assert (not rstk_we = '1') or (((is_instr.alu = '1' and instruction(6) = '1') or is_instr.call = '1')) severity failure;
217assert (not dstk_we = '1') or (((is_instr.alu = '1' and instruction(7) = '1') or is_instr.lit = '1')) severity failure;
218
219pc_c <= pc_n after delay;
220stop_c <= stop_n after delay;
221vstkp_c <= vstkp_n after delay;
222rstkp_c <= rstkp_n after delay;
223tos_c <= tos_n after delay;
224irq_addr_c <= irq_addr_n after delay;
225irq_en_c <= irq_en_n after delay;
226irq_c <= irq_n after delay;
227end if;
228end if;
229end process;
230
231stack_write: process(clk)
232begin
233if rising_edge(clk) then
234if dstk_we = '1' then
235vstk_ram(to_integer(vstkp_n)) <= tos_c after delay;
236end if;
237if rstk_we = '1' then
238rstk_ram(to_integer(rstkp_n)) <= rstk_data after delay;
239end if;
240end if;
241end process;
242
243decode: process(insn, irq_addr_c, is_interrupt, stop_c, pc_c)
244begin
245if stop_c = '1' then -- assert a BRANCH instruction to current location on CPU halt
246instruction <= "000" & pc_c after delay;
247elsif is_interrupt = '1' then -- assemble a CALL instruction on interrupt
248instruction <= (others => '0') after delay;
249instruction(15 downto 13) <= "010" after delay; -- turn into a CALL
250instruction(irq_addr_c'range) <= irq_addr_c after delay; -- address to call
251else
252instruction <= insn after delay;
253end if;
254end process;
255
256alu_select: process(instruction, is_instr)
257begin
258if is_instr.lit = '1' then
259aluop <= "10101" after delay;
260elsif is_instr.branch0 = '1' then
261aluop <= (0 => '1', others => '0') after delay;
262elsif is_instr.alu = '1' then
263aluop <= instruction(12 downto 8) after delay;
264else
265aluop <= (others => '0') after delay;
266end if;
267end process;
268
269alu_unit: process(
270tos_c, nos, rtos_c,
271din, instruction, aluop,
272io_din,
273vstkp_c, rstkp_c,
274compare,
275irq_en_c)
276begin
277io_re <= '0'; -- hardware reads can have side effects
278tos_n <= tos_c;
279irq_en_n <= irq_en_c;
280case aluop is
281-- Register Operations
282when "00000" => tos_n <= tos_c after delay;
283when "00001" => tos_n <= nos after delay;
284when "01011" => tos_n <= rtos_c after delay;
285when "10100" => tos_n <= cpu_id after delay;
286when "10101" => tos_n <= "0" & instruction(14 downto 0) after delay; -- undocumented, may be removed
287-- Logical Operations
288when "00011" => tos_n <= tos_c and nos after delay;
289when "00100" => tos_n <= tos_c or nos after delay;
290when "00101" => tos_n <= tos_c xor nos after delay;
291when "00110" => tos_n <= not tos_c after delay;
292-- Comparison Operations
293when "00111" => tos_n <= (others => compare.equal) after delay;
294when "01000" => tos_n <= (others => compare.more) after delay;
295when "01111" => tos_n <= (others => compare.umore) after delay;
296when "10011" => tos_n <= (others => compare.zero) after delay;
297-- Arithmetic Operations
298when "01001" => tos_n <= word(unsigned(nos) srl to_integer(unsigned(tos_c(3 downto 0)))) after delay;
299when "01101" => tos_n <= word(unsigned(nos) sll to_integer(unsigned(tos_c(3 downto 0)))) after delay;
300when "00010" => tos_n <= word(unsigned(nos) + unsigned(tos_c)) after delay;
301when "01010" => tos_n <= word(unsigned(tos_c) - 1) after delay;
302-- Input (output is handled elsewhere)
303when "01100" => -- input: 0x4000 - 0x7FFF is external input
304if tos_c(15 downto 14) /= "00" then
305tos_n <= io_din after delay;
306io_re <= '1' after delay;
307else
308tos_n <= din after delay;
309end if;
310-- Stack Depth
311when "01110" => tos_n <= (others => '0') after delay;
312tos_n(vstkp_c'range) <= std_ulogic_vector(vstkp_c) after delay;
313when "10010" => tos_n <= (others => '0') after delay;
314tos_n(rstkp_c'range) <= std_ulogic_vector(rstkp_c) after delay;
315-- CPU Status Set/Get
316when "10001" => tos_n <= (others => '0') after delay;
317tos_n(0) <= irq_en_c after delay;
318when "10000" => tos_n <= nos after delay;
319irq_en_n <= tos_c(0) after delay;
320-- Default/Invalid instructions
321when others => tos_n <= tos_c after delay;
322report "Invalid ALU operation: " & integer'image(to_integer(unsigned(aluop))) severity error;
323end case;
324end process;
325
326stack_update: process(
327pc_c, instruction, tos_c,
328vstkp_c, dd,
329rstkp_c, rd,
330is_instr, pc_plus_one, is_interrupt)
331begin
332vstkp_n <= vstkp_c;
333rstkp_n <= rstkp_c;
334rstk_we <= '0';
335rstk_data <= "00" & pc_plus_one & "0";
336
337if is_instr.lit = '1' then
338assert to_integer(vstkp_c) + 1 < stack_size;
339vstkp_n <= vstkp_c + 1 after delay;
340end if;
341if is_instr.alu = '1' then
342assert (not instruction(6) = '1') or ((to_integer(rstkp_c) + to_integer(signed(rd))) < stack_size);
343assert ((to_integer(vstkp_c) + to_integer(signed(dd))) < stack_size);
344rstk_we <= instruction(6) after delay;
345rstk_data <= tos_c after delay;
346vstkp_n <= vstkp_c + unsigned(dd) after delay;
347rstkp_n <= rstkp_c + unsigned(rd) after delay;
348end if;
349if is_instr.branch0 = '1' then
350vstkp_n <= (vstkp_c - 1) after delay;
351end if;
352if is_instr.call = '1' then
353if is_interrupt = '1' then
354rstk_data <= "00" & pc_c & "0" after delay;
355end if;
356rstkp_n <= rstkp_c + 1 after delay;
357rstk_we <= '1' after delay;
358end if;
359end process;
360
361pc_update: process(
362instruction, rtos_c, pc_plus_one,
363is_instr,
364compare.zero)
365begin
366if is_instr.branch = '1' or (is_instr.branch0 = '1' and compare.zero = '1') or is_instr.call = '1' then
367pc_n <= instruction(12 downto 0) after delay;
368elsif is_instr.alu = '1' and instruction(4) = '1' then
369pc_n <= rtos_c(13 downto 1) after delay;
370else
371pc_n <= pc_plus_one after delay;
372end if;
373end process;
374end architecture;
375
376