forth-cpu

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--------------------------------------------------------------------------------
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--| @file core.vhd
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--| @brief This contains the CPU, memory and interrupt handler instances
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--|
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--| @author     Richard James Howe.
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--| @copyright  Copyright 2013,2017 Richard James Howe.
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--| @license    MIT
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--| @email      howe.r.j.89@gmail.com
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--|
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--------------------------------------------------------------------------------
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library ieee, work;
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use ieee.std_logic_1164.all;
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use work.util.n_bits;
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use work.util.common_generics;
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use work.h2_pkg.all;
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package core_pkg is
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	type cpu_debug_interface is record
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		pc:        address;
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		insn:      word;
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		dwe:       std_ulogic;
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		dre:       std_ulogic;
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		din:       word;
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		dout:      word;
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		daddr:     address;
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	end record;
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	component core is
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	generic(g: common_generics; number_of_interrupts: positive := 8);
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	port(
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		-- synthesis translate_off
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		debug:           out cpu_debug_interface;
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		-- synthesis translate_on
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		clk:             in   std_ulogic;
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		rst:             in   std_ulogic;
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		stop:            in   std_ulogic; -- Halts the CPU
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		io_wr:           out  std_ulogic; -- I/O Write enable
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		io_re:           out  std_ulogic; -- hardware *READS* can have side effects
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		io_din:          in   word;
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		io_dout:         out  word:= (others => 'X');
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		io_daddr:        out  word:= (others => 'X');
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		-- Interrupts
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		cpu_irc:         in std_ulogic_vector(number_of_interrupts - 1 downto 0);
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		cpu_irc_mask:    in std_ulogic_vector(number_of_interrupts - 1 downto 0);
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		cpu_irc_mask_we: in std_ulogic);
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	end component;
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	component interrupt_request_handler is
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	generic(
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		g: common_generics;
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		number_of_interrupts:   positive := 8;
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		lowest_interrupt_first: boolean  := true);
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	port(
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		clk:     in  std_ulogic;
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		rst:     in  std_ulogic;
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		irq_i:   in  std_ulogic;
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		irc_i:   in  std_ulogic_vector(number_of_interrupts - 1 downto 0);
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		mask:    in  std_ulogic_vector(number_of_interrupts - 1 downto 0);
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		mask_we: in  std_ulogic;
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		irq_o:   out std_ulogic;
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		addr_o:  out std_ulogic_vector(n_bits(number_of_interrupts) - 1 downto 0));
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	end component;
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end package;
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----- CPU ----------------------------------------------------------------------
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library ieee,work;
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use ieee.std_logic_1164.all;
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use work.core_pkg.all;
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use work.h2_pkg.all;
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use work.util.n_bits;
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use work.util.common_generics;
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use work.util.file_format;
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use work.util.file_hex;
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use work.util.or_reduce;
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entity core is
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	generic(g: common_generics; number_of_interrupts: positive := 8);
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	port(
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		-- synthesis translate_off
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		debug:           out cpu_debug_interface;
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		-- synthesis translate_on
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		clk:             in   std_ulogic;
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		rst:             in   std_ulogic;
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		stop:            in   std_ulogic; -- Halts the CPU
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		io_wr:           out  std_ulogic; -- I/O Write enable
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		io_re:           out  std_ulogic; -- hardware *READS* can have side effects
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		io_din:          in   word;
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		io_dout:         out  word := (others => 'X');
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		io_daddr:        out  word := (others => 'X');
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		-- Interrupts
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		cpu_irc:         in std_ulogic_vector(number_of_interrupts - 1 downto 0);
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		cpu_irc_mask:    in std_ulogic_vector(number_of_interrupts - 1 downto 0);
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		cpu_irc_mask_we: in std_ulogic);
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end;
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architecture structural of core is
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	constant interrupt_address_length: natural     := n_bits(number_of_interrupts);
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	constant file_name:                string      := "h2.hex";
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	constant file_type:                file_format := file_hex;
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	signal pc:    address    := (others => '0'); -- Program counter
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	signal insn:  word       := (others => '0'); -- Instruction issued by program counter
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	signal dwe:   std_ulogic := '0'; -- Write enable
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	signal dre:   std_ulogic := '0'; -- Read enable
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	signal din:   word       := (others => '0');
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	signal dout:  word       := (others => '0');
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	signal daddr: address    := (others => '0');
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	signal irc_edges:    std_ulogic_vector(cpu_irc'range) := (others => '0');
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	signal irq_edges:    std_ulogic := '0';
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	signal h2_irq:       std_ulogic := '0';
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	signal h2_irq_addr:  std_ulogic_vector(interrupt_address_length - 1 downto 0) := (others=>'0');
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begin
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	-- synthesis translate_off
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	debug.pc    <= pc;
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	debug.insn  <= insn;
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	debug.dwe   <= dwe;
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	debug.dre   <= dre;
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	debug.din   <= din;
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	debug.dout  <= dout;
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	debug.daddr <= daddr;
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	-- synthesis translate_on
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	-- Ensure all interrupts occur are rising edge triggered
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	edges: work.util.rising_edge_detectors
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	generic map(g => g, N => cpu_irc'length)
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	port map(
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		clk   => clk,
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		rst   => rst,
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		di    => cpu_irc,
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		do    => irc_edges);
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	irq_edges <= or_reduce(irc_edges);
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	irqh_0: work.core_pkg.interrupt_request_handler
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	generic map(g => g, number_of_interrupts => number_of_interrupts)
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	port map(
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		clk    => clk,
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		rst    => rst,
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		irq_i  => irq_edges,
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		irc_i  => irc_edges,
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		irq_o  => h2_irq,
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		addr_o => h2_irq_addr,
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		mask    => cpu_irc_mask,
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		mask_we => cpu_irc_mask_we);
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	h2_0: work.h2_pkg.h2 -- The actual CPU instance (H2)
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	generic map(asynchronous_reset => g.asynchronous_reset, delay => g.delay, interrupt_address_length => interrupt_address_length)
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	port map(
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		clk       =>    clk,
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		rst       =>    rst,
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		-- External interface with the 'outside world'
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		stop      =>  stop,
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		io_wr     =>  io_wr,
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		io_re     =>  io_re,
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		io_din    =>  io_din,
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		io_dout   =>  io_dout,
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		io_daddr  =>  io_daddr,
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		irq       =>  h2_irq,
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		irq_addr  =>  h2_irq_addr,
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		-- Instruction and instruction address to CPU
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		pc        =>  pc,
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		insn      =>  insn,
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		-- Fetch/Store
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		dwe       =>  dwe,
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		dre       =>  dre,
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		din       =>  din,
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		dout      =>  dout,
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		daddr     =>  daddr);
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	mem_h2_0: entity work.dual_port_block_ram
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	generic map(
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		g             => g,
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		addr_length   => address'length,
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		data_length   => word'length,
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		file_name     => file_name,
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		file_type     => file_type)
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	port map(
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		-- Port A, Read only, CPU instruction/address
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		a_clk   =>    clk,
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		a_dwe   =>    '0',
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		a_dre   =>    '1',
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		a_addr  =>    pc,
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		a_din   =>    (others => '0'),
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		a_dout  =>    insn,
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		-- Port B, Read/Write controlled by CPU instructions
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		b_clk   =>    clk,
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		b_dwe   =>    dwe,
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		b_dre   =>    dre,
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		b_addr  =>    daddr,
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		b_din   =>    dout,
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		b_dout  =>    din);
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end architecture;
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--------------------------------------------------------------------------------
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--| @brief Interrupt request handler, while the CPU can handle interrupts
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--|        it does not to a good job of it. This allows customization of
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--|        priority.
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--|
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--| @author     Richard James Howe.
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--| @copyright  Copyright 2017, 2019 Richard James Howe.
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--| @license    MIT
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--| @email      howe.r.j.89@gmail.com
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--|
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--| This is a simple interrupt handler, interrupts are decoded in priority
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--| order which can be set by a generic. If an interrupt occurs and then
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--| another interrupt of occurs before it has been processed the second
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--| interrupt will be lost.
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--|
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--------------------------------------------------------------------------------
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library ieee,work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all; -- only needed for calculations relating to generics
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use work.util.reg;
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use work.util.n_bits;
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use work.util.select_bit;
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use work.util.priority;
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use work.util.common_generics;
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entity interrupt_request_handler is
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	generic(
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		g: common_generics;
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		number_of_interrupts:   positive := 8;
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		lowest_interrupt_first: boolean  := true);
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	port(
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		clk:     in  std_ulogic;
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		rst:     in  std_ulogic;
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		irq_i:   in  std_ulogic;
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		irc_i:   in  std_ulogic_vector(number_of_interrupts - 1 downto 0);
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		mask:    in  std_ulogic_vector(number_of_interrupts - 1 downto 0);
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		mask_we: in  std_ulogic;
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		irq_o:   out std_ulogic;
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		addr_o:  out std_ulogic_vector(n_bits(number_of_interrupts) - 1 downto 0));
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end;
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architecture rtl of interrupt_request_handler is
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	constant addr_length: natural := n_bits(number_of_interrupts);
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	signal irq_n: std_ulogic := '0';
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	signal irc_n: std_ulogic_vector(irc_i'range) := (others => '0');
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	signal addr:  std_ulogic_vector(addr_length - 1 downto 0) := (others => '0');
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	signal irq:   std_ulogic := '0';
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	signal mask_n: std_ulogic_vector(mask'range) := (others => '0');
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begin
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	irq_in: entity work.reg
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		generic map(g => g, N  => 1)
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		port map(
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			clk    =>  clk,
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			rst    =>  rst,
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			we     =>  '1',
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			di(0)  =>  irq_i,
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			do(0)  =>  irq_n);
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	irc_in: entity work.reg
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		generic map(g => g, N  => number_of_interrupts)
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		port map(
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			clk  =>  clk,
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			rst  =>  rst,
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			we   =>  '1',
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			di   =>  irc_i,
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			do   =>  irc_n);
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	irc_mask: entity work.reg generic map(g => g, N  => number_of_interrupts)
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		port map(
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			clk  =>  clk,
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			rst  =>  rst,
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			we   =>  mask_we,
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			di   =>  mask,
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			do   =>  mask_n);
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	process(irc_n, irq_n, mask_n)
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		variable addr_n: std_ulogic_vector(addr'range) := (others => '0');
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	begin
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		addr_n := priority(irc_n, not lowest_interrupt_first);
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		addr_o <= addr_n after g.delay;
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		if select_bit(mask_n, addr_n) = '1' then
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			irq_o <= irq_n after g.delay;
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		else
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			irq_o <= '0' after g.delay;
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		end if;
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	end process;
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end architecture;
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