master
clockintr: remove clockintr_init(), clockintr_flags
move simplebusvar.h so it can be used without ifdef ok kettenis@ phessler@
Constify struct cfattach.
don't need to put config_activate_children inside cfattach, because NULL means the same ok kettenis
Add a cortex bus which represents the ARM MPCore Complex. It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cache controller can be added. The base address for those controllers are figured out using the periphbase register.
Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is an extension to the GIC controller, which is represented as subnode in the device tree. There can be multiple GICv2Ms, so it makes sense to attach those to ampintc(4) as some kind of simplebus. The GICv2M is simply an interrupt generator that can be used by PCIe devices to ring the door bell. There is no need for further configuration, we only need to find out which SPIs we are allowed to use for MSI and to register an edge triggered interrupt on a (randomly) allocated SPI.
Add a secure monitor call function, so that a secondary cache controller driver can talk to its controller properly.