master
Added a couple of test cases.
lspci: Decode "VGA 16-bit decode" in bridge control register
Added a test case for broken extended capabilities
Added decoding of HT MSI capability.
lspci: fix "suprise" typo
lspci: Include "ECRC" in the ECRC generate/check labels
lspci: Decode AER Multiple Header and TLP Prefix Log bits
lspci: Dump AER Header Log
lspci: Decode AER Root Error Command, Root Error Status, Error Source
pciutils: Add test case for pci atomic ops
Flit Mode and Device 3 Capability
pciutils: Add decode support for Data Object Exchange Extended Capability
Update DPC tests/cap-dpc
lspci: Add test case for CXL device
lspci: Update tests files with VF 10-Bit Tag Requester
lspci: Decode only supported ASPM exit latencies
lspci: Decode all defined fields in the Device Capabilities 2 register
lspci: Decode PCIe Link Capabilities 2, expand Link Status 2
lspci: Decode "Slot Implemented" for PCI/PCI-X to PCIe Bridges
lspci: add test with capabilities 32, 34, and 36
lspci: Avoid "%1$c" style format strings in HT capability
ls-ecaps: Add XT and TEE-Limited support reporting
pciutils: Update the tests/cap-l1-pm with actual device data
lspci: Decode Multicast Extended Capability
Decode PASID and PRI extended capabilities
Added a test case for the PCI AF capability
Fix spelling of surprise
lspci: Add test case for Physical Layer 16 GT/s and 32 GT/s extended capability registers
lspci: Add test case for PTM
pciutils: Add decode support for RCECs
lspci: Decode the (virtual) resizeble BAR capability
Added a test case for Virtual Channel and Root Complex Link caps
Added a test case for the VC capability with a port arbitration table
lspci: add VirtIO SharedMemory capability support
Subject: lspci: Display PASID required attribute in Page Status Register.
Added test cases for topology computation
Add test case with multidomain Freescale P2020 PCIe hierarchy