master
pyTICL: TICL barrel iteration
pyTICL: CPU/GPU (alpaka) backend selection
pyTICL: orchestrate HGCAL local reco + layer clustering with TICL
pyTICL: validated, type-safe TICL configuration framework (v5 core)
pyTICL: generate the TICL Event Content from the assembled graph
pyTICL: add Phase-2 HLT target
pyTICL: Graphviz export of the assembled module graph (to_dot / show_graph)
pyTICL: track CMSSW_20_1_X IB (HLT pfTICL MTD-timing inputs)
pyTICL: track baseline CLUE3DBarrel algo_verbosity (debug 9999 removed)
pyTICL: single-source-of-truth validation derivation