master
Pretty major change where all 'addr's went to addr_t. I dont know what I was thinking when I made the addr typedef.
Get the ARM port building again. Doesn't work, but builds
more work in progress on x86_64
Start getting the ppc build to work again
Some SH4 (Dreamcast) work in progress
more x86_64 stuff: -most of the mmu code is implemented -fix up the bad swap_stacks_and_call -fix up the tss stuff -fix the interrupt glue (needs iretq)
-added cpuid support to determine x86 cpu capabilities -enabled page global bit if the cpu supports it -use fxsave on context switch if it's supported
massive ppc checkin. not quite finshed yet, but threading and vm stuff is up and running
Remove a space in the INC_ARCH macro that screws up any chance of compiling on gcc 3.2
-Changed most of the header guard strings to be a little more verbose -Added include/arch/cpu.h which contains PAGE_SIZE and BIG/LITTLE endian macros
Remap all of the io interrupt handlers to base 0 instead of base 0x20 on x86. This lets some drivers be more portable across architectures, since they dont have to add 0x20 to the int_set_io_interrupt_handler() call.
Fix an old massive problem with the timers. It turns out that the code that tests the speed of the apic clock de-configures cpu 0's local apic so that the local apic timer doesn't run on that node. This was covered up by the fact that the isa timer was left running on that node so cpu 0 would still get timer interrupts occasionally. In the past this didn't matter so much because it didn't matter how often each cpu got the timer interrupts, as long as they ocurred at a reasonable rate. The new time-keeping mechanism does require they come in at a fixed rate on cpu 0, however.
refactor some of the context switch code into arch independant source
Read the RTC clock on PCs at bootup so we can tell what time it really is.
rearchitecture of the way time is kept:
convert the internal pagedir list in the x86 vm_translation_map code to the generic list macro.