embox

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/**
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 * @file
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 *
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 * @date 21.02.13
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 * @author Pavel Cherstvov
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 */
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#include <embox/unit.h>
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#include <sys/types.h>
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#include <stdio.h>
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#include <hal/reg.h>
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//#include <kernel/irq.h> 		/* IRQ is coming soon */
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//#include <drivers/irqctrl.h> 	/* IRQ is coming soon */
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#include <drivers/dm37xx_mux.h>
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#include "omap3_spi_poll.h"
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EMBOX_UNIT_INIT(omap3_spi_poll_init);
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int spi_poll_switch_master_mode(void) {
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	REG_ORIN(MCSPI1_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET);
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	while (!(REG_LOAD(MCSPI1_SYSSTATUS) & MCSPI_SYSSTATUS_RESETDONE)) {
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	}
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	REG_CLEAR_BIT(MCSPI1_CHxCONF(SPI_CHANNEL_NR), 18); /* IS, somi reception*/
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	REG_SET_BIT(MCSPI1_CHxCONF(SPI_CHANNEL_NR), 16); /* DPE0, no trans on somi */
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	REG_CLEAR_BIT(MCSPI1_CHxCONF(SPI_CHANNEL_NR), 17); /* DPE1 1, transmission on simo */
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	REG_CLEAR_BIT(MCSPI1_CHxCONF(SPI_CHANNEL_NR), 12); /* TRM, transmit and receive mode */
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	REG_CLEAR_BIT(MCSPI1_CHxCONF(SPI_CHANNEL_NR), 13); /* TRM, transmit and receive mode */
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	REG_ORIN(MCSPI1_CHxCONF(SPI_CHANNEL_NR), ( 0x7 << 7)); /* WL, word length 8 bits*/
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	REG_SET_BIT(MCSPI1_CHxCONF(SPI_CHANNEL_NR), 6); /* EPOL, cs active polarity low */
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	REG_ORIN(MCSPI1_CHxCONF(SPI_CHANNEL_NR), ( 0x8 << 2)); /* CLKD, divider 256 (~187 kHz) */
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	REG_CLEAR_BIT(MCSPI1_CHxCONF(SPI_CHANNEL_NR), 1); /* POL, 0 */
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	REG_CLEAR_BIT(MCSPI1_CHxCONF(SPI_CHANNEL_NR), 0); /* PHA, 0 */
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	REG_CLEAR_BIT(MCSPI1_MODULCTRL, 2); /* MS, Master mode */
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	REG_SET_BIT(MCSPI1_CHxCTRL(SPI_CHANNEL_NR), 0); /* EN, channel SPI_CHANNEL_NR enabled */
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	return 0;
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}
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static int omap3_spi_poll_init(void) {
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	REG_ORIN(CM_FCLKEN1_CORE, (1 << 18));
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	REG_ORIN(CM_ICLKEN1_CORE, (1 << 18));
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	MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PD | M0 )); /* mcspi1_clk */
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	MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PD | M0 )); /* mcspi1_cs0 */
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	MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PD | M0 )); /* mcspi1_simo */
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	MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PD | M0 )); /* mcspi1_somi */
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	REG_SET_BIT(CM_ICLKEN_PER,17);
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	REG_SET_BIT(CM_FCLKEN_PER,17);
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	REG_ORIN(GPIO6_SYSCONFIG, GPIO6_SYSCONFIG_SOFTRESET);
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	while (!(REG_LOAD(GPIO6_SYSSTATUS) & GPIO6_SYSSTATUS_RESETDONE)) {
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	}
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	MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | PU | M4 )); /* gpio_162 */
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	REG_CLEAR_BIT(GPIO6_OE,2);
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	REG_SET_BIT(GPIO6_CLEARDATAOUT,2); /* switch on-module chip select muxing to CS1 */
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	return 0;
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}
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#if 0
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/* IRQ is coming soon */
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static irq_return_t my_isr(unsigned int my_irq_nr, void *my_dev_id) {
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	return IRQ_HANDLED;
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}
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#endif
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int spi_poll_send(const char *outdata, __u8 *indata, __u32 nBytes) {
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	REG_ORIN(MCSPI1_IRQSTATUS, MCSPI_IRQSTATUS_TXEMPTY(SPI_CHANNEL_NR));
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	REG_ORIN(MCSPI1_IRQSTATUS, MCSPI_IRQSTATUS_RXFULL(SPI_CHANNEL_NR));
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	while (nBytes) {
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		REG_STORE(MCSPI1_TX(SPI_CHANNEL_NR), *outdata);
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		while (!(REG_LOAD(MCSPI1_IRQSTATUS) & MCSPI_IRQSTATUS_TXEMPTY(SPI_CHANNEL_NR))) {
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				}
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		while (!(REG_LOAD(MCSPI1_IRQSTATUS) & MCSPI_IRQSTATUS_RXFULL(SPI_CHANNEL_NR))) {
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				}
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		*indata = REG_LOAD(MCSPI1_RX(SPI_CHANNEL_NR));
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		REG_ORIN(MCSPI1_IRQSTATUS, MCSPI_IRQSTATUS_RXFULL(SPI_CHANNEL_NR));
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		REG_ORIN(MCSPI1_IRQSTATUS, MCSPI_IRQSTATUS_TXEMPTY(SPI_CHANNEL_NR));
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		nBytes--;
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		outdata++;
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		indata++;
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	}
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	return 0;
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}
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