embox

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/**
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 * @file bcm283x_spi0.c
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 * @brief 
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 * @author kpishere
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 * @version 0.1
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 * @date 2021.07.16
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 */
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#include <errno.h>
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#include <drivers/common/memory.h>
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#include <drivers/spi.h>
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#include <embox/unit.h>
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#include <framework/mod/options.h>
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#include <hal/reg.h>
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#include <util/log.h>
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#include <util/math.h>
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#include <kernel/printk.h>
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#include <asm/delay.h>
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#include <assert.h>
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#include <drivers/dma/pl330_dma.h>
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#include <drivers/gpio/gpio.h>
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#include <drivers/gpio/bcm283x/bcm283x_gpio.h>
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#include <drivers/spi.h>
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#include "bcm283x_spi0.h"
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#include "bcm283x_spi_dev.h"
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#define PBASE                     OPTION_GET(NUMBER,base_addr)
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#define SPI_BUS_CLOCK_DIVISOR     OPTION_GET(NUMBER,spi_bus_clock_divisor)
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#define SPI_INT0                  OPTION_GET(NUMBER,spi_int)
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// command block must be 256 bit aligned in memory
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#define MEM_ALGN_256 (0x00000020)
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// Toggle an extra GPIO pin at various points to debug/test timing
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#if 0
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    #define DRIVER_TESTING
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    #define PIN ( 1 << 25 )
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#endif
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/* Errata to BCM2835 behaviour: documentation states that the SPI0 DLEN register is only used for DMA. 
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 * However, even when DMA is not being utilized, setting it from a value != 0 or 1 gets rid of an 
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 * excess idle clock cycle that is present when transmitting each byte. (by default in Polled SPI 
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 * Mode each 8 bits transfer in 9 clocks) With DLEN=2 each byte is clocked to the bus in 8 cycles, 
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 * observed to improve max throughput from 56.8mbps to 63.3mbps (+11.4%, quite close to the 
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 * theoretical +12.5%)
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 * https://www.raspberrypi.org/forums/viewtopic.php?f=44&t=181154
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 */
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#define DLEN_NO_DMA_VALUE 2;
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struct bcm283x_spi_regs {
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    uint32_t cs; /* SPI Master Control and Status */
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/* RW: DMA Mode (DMAEN set)
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    If TA is clear, the first 32-bit write to this register will control 
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    SPIDLEN and SPICS. Subsequent reads and writes will be taken as 
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    four-byte data words to be read/written to the FIFOs Poll/Interrupt 
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    Mode (DMAEN clear, TA set) Writes to the register write bytes to TX FIFO. 
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    Reads from register read bytes from the RX FIFO
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 */
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    uint32_t fifo; /* SPI Master TX and RX FIFOs */
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/* RW: 15:0 Clock Divider SCLK = Core Clock / CDIV
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    If CDIV is set to 0, the divisor is 65536. The divisor must be a power of 2.
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    Odd numbers rounded down. The maximum SPI clock rate is of the APB clock.
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 */
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    uint32_t clk; /* SPI Master Clock Divider */
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/* RW: 15:0 Data Length - The number of bytes to transfer.
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    This field is only valid for DMA mode (DMAEN set) and controls how many bytes 
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    to transmit (and therefore receive).
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 */     
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    uint32_t dlen; /* SPI Master Data Length */
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/* RW: 3:0 This sets the Output Hold delay in APB clocks. A value of 0 causes a 1 clock delay. */
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    uint32_t ltoh; /* SPI LOSSI mode TOH */
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/* RW: This register controls the generation of the DREQ and Panic signals to an 
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    external DMA engine The DREQ signals are generated when the FIFOs reach their 
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    defined levels and need servicing. The Panic signals instruct the external DMA engine 
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    to raise the priority of its AXI requests.*/
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    uint32_t dc; /* SPI DMA DREQ Controls */
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};
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#define REGS_SPI0 ((struct bcm283x_spi_regs *)(PBASE))
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#define BCM283X_SPI0_TX_FIFO_LEN (16*sizeof(uint32_t))
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#define BCM283X_SPI0_RX_FIFO_LEN (16*sizeof(uint32_t))
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#define BCM283X_SPI0_TX_FIFO_FL  (4*sizeof(uint32_t))
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#define BCM283X_SPI0_RX_FIFO_HW  (3*sizeof(uint32_t))
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#define BCM283X_PRIV(x) ((struct bcm283x_spi_dev *)(x)->priv)
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static int bcm283x_spi0_init(void) {
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    uint32_t pins_spi_Alt0 =( 1 << 7 ) | ( 1 << 8 ) | ( 1 << 9 ) | ( 1 << 10 ) | ( 1 << 11 );    
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    gpio_setup_mode(GPIO_PORT_A, pins_spi_Alt0, GPIO_MODE_OUT_ALTERNATE | GPIO_ALTERNATE(GFAlt0) );
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#ifdef DRIVER_TESTING
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    gpio_setup_mode(GPIO_PORT_A, PIN, GPIO_MODE_OUTPUT);
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#endif
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    // Initialize the Control and Status register to defaults:
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    //CS=0 (Chip Select), CPHA=0 (Clock Phase), CPOL=0 (Clock Polarity), 
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    //CSPOL=0 (Chip Select Polarity), TA=0 (Transfer not active), and reset TX and RX queues.
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    REGS_SPI0->cs = SPI0_CS(0);
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    REGS_SPI0->clk = SPI_BUS_CLOCK_DIVISOR;
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    REGS_SPI0->dlen = DLEN_NO_DMA_VALUE;
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    return 0;
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}
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static irq_return_t bcm283x_spi_intrd_irq_handler(unsigned int irq_nr, void *data);
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static int bcm283x_spi0_attach(struct spi_device *dev) {
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    int res = 0;
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    if( !(REGS_SPI0->cs & SPI0_CS_INTD) && !(REGS_SPI0->cs & SPI0_CS_INTR) ) {
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        res = irq_attach(SPI_INT0, bcm283x_spi_intrd_irq_handler, 0x00, dev, "SPI0 IRQ");
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    }
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    return res;
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}
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static int bcm283x_spi0_select(struct spi_device *dev, int cs) {
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    int res = 0;
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    if (cs < 0 || cs > 3) {
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        log_error("Only cs=0..3 are avalable!");
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        return -EINVAL;
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    }
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    if( dev->flags & SPI_CS_ACTIVE ) {
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    }
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    if( dev->flags & SPI_CS_INACTIVE ) {
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    }
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    // If flag set for either interrupt option, register interrupt function
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    if( dev->flags & SPI_CS_IRQD ) {   
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        res = bcm283x_spi0_attach(dev);     
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        REGS_SPI0->cs |= SPI0_CS_INTD;
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    }
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    if( dev->flags & SPI_CS_IRQR ) {        
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        res = bcm283x_spi0_attach(dev);     
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        REGS_SPI0->cs |= SPI0_CS_INTR;
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    }
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    // If no flags set for interrupt, detatch interrupt
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    if( !(dev->flags & SPI_CS_IRQR) && !(dev->flags & SPI_CS_IRQD)
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        && irq_nr_valid(SPI_INT0) == 0 ) {
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        res = irq_detach(SPI_INT0, dev);
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    }
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    // Enable DMA
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    if( dev->flags & SPI_CS_DMAEN 
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        && !(REGS_SPI0->cs & SPI0_CS_DMAEN) ) {
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        assert( BCM283X_PRIV(dev)->dma_chan_out != BCM283X_PRIV(dev)->dma_chan_in );
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        REGS_SPI0->cs |= SPI0_CS_DMAEN;
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        REGS_SPI0->dc = BCM283X_PRIV(dev)->dma_levels;
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        /* Set Panic and Priority levels at High 2/3rds and then Low 1/3rd respectively
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         * If they are not set, DMA_LEVELS() must be about double higher.
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         */
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        dma_config_extended(BCM283X_PRIV(dev)->dma_chan_in, NULL, DMA_CS_PANIC_PRIORITY(0x0C) | DMA_CS_PRIORITY(0x06) );
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        // Channel out receives data from SPI fifo to memory in    
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        dma_config_extended(BCM283X_PRIV(dev)->dma_chan_out, BCM283X_PRIV(dev)->dma_complete,
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        		DMA_CS_PANIC_PRIORITY(0x0C) | DMA_CS_PRIORITY(0x06));
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    }
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    // If no flags set for interrupt, cause interrupt to detatch
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    if( !(dev->flags & SPI_CS_DMAEN) && (REGS_SPI0->cs & SPI0_CS_DMAEN) ) {
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        dma_config_extended(BCM283X_PRIV(dev)->dma_chan_out, NULL, 0x00);
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        REGS_SPI0->cs &= ~( SPI0_CS_DMAEN );
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    }
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    // set default CPHA=0 (Clock Phase), CPOL=0 (Clock Polarity)
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    REGS_SPI0->cs &= ~(SPI0_CS_CPOL | SPI0_CS_CPHA); 
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    if(dev->flags & SPI_CS_MODE(SPI_MODE_1)) REGS_SPI0->cs |= SPI0_CS_CPHA;
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    if(dev->flags & SPI_CS_MODE(SPI_MODE_2)) REGS_SPI0->cs |= SPI0_CS_CPOL;
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    // A clock divisor value is set
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    if( (dev->flags >> 16) ) {
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        REGS_SPI0->clk = (dev->flags >> 16);
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    }
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    // Set the CS lines
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    REGS_SPI0->cs &= ~SPI0_CS(0xFF);
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    REGS_SPI0->cs |= SPI0_CS(cs);
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    // Set the CS hold delay
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    REGS_SPI0->ltoh = 0;
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    return res;
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}
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static int bcm283x_spi0_do_transfer(struct spi_device *dev, uint8_t *inbuf
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        , uint8_t *outbuf, int tx_count, int rx_count) {
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    int tx_cnt, rx_cnt;
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    irq_lock();
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    tx_cnt = rx_cnt = 0;
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    /* Do not add log_debug() or some another stuff here, */
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    while ( ( tx_cnt < tx_count && inbuf != NULL ) 
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        ||  (rx_cnt < rx_count && outbuf != NULL ) ) {
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        if(tx_cnt < tx_count ) {
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            if( inbuf != NULL ) {
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                // Wait for FIFO to have 1-byte space    
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                while( !(REGS_SPI0->cs & SPI0_CS_TXD) ) {
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#ifdef DRIVER_TESTING
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                    gpio_set(GPIO_PORT_A, PIN, GPIO_PIN_HIGH );
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                    gpio_set(GPIO_PORT_A, PIN, GPIO_PIN_LOW );
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#endif
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                }; 
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                REGS_SPI0->fifo = inbuf[tx_cnt++];
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            } else { 
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                // write without waiting for buffer ready
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                REGS_SPI0->fifo = 0x00;
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            }
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        }
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        if( rx_cnt < rx_count && outbuf != NULL ) {
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            while ( !(REGS_SPI0->cs & SPI0_CS_RXD) ); // Wait for rx byte
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            outbuf[rx_cnt++] = REGS_SPI0->fifo;
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        }
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    }
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    // read out FIFO incoming buffer
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    while( REGS_SPI0->cs & SPI0_CS_RXD ) { 
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        uint32_t discard;
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        discard += REGS_SPI0->fifo;    
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    }
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    // Wait for tx to complete
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    while( !(REGS_SPI0->cs & SPI0_CS_DONE) ) {
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#ifdef DRIVER_TESTING
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        gpio_set(GPIO_PORT_A, PIN, GPIO_PIN_HIGH );
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        gpio_set(GPIO_PORT_A, PIN, GPIO_PIN_LOW );
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#endif
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    };   
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    irq_unlock();
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    return max(tx_cnt, rx_cnt);         
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}
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// Interrupt for data send required or complete
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static irq_return_t bcm283x_spi_intrd_irq_handler(unsigned int irq_nr, void *data) {
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	irq_return_t ret = IRQ_HANDLED;
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	struct spi_device *dev = (struct spi_device*) data;
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	// Transmit and receive with CS asserted
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	if ((REGS_SPI0->cs & (SPI0_CS_DONE | SPI0_CS_TA))
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			&& BCM283X_PRIV(dev)->count > 0) {
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		BCM283X_PRIV(dev)->count -= bcm283x_spi0_do_transfer(dev,
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		BCM283X_PRIV(dev)->in, BCM283X_PRIV(dev)->out,
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				min(BCM283X_SPI0_TX_FIFO_FL, BCM283X_PRIV(dev)->count),
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				min(BCM283X_SPI0_TX_FIFO_FL, BCM283X_PRIV(dev)->count));
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		if (BCM283X_PRIV(dev)->count <= 0) {
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			REGS_SPI0->cs &= ~SPI0_CS_TA; // De-assert
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		}
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		if (BCM283X_PRIV(dev)->send_complete && BCM283X_PRIV(dev)->count <= 0) {
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			BCM283X_PRIV(dev)->send_complete(dev, BCM283X_PRIV(dev)->count);
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		}
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	}
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	// Receive with CS un-asserted
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	if ((REGS_SPI0->cs & SPI0_CS_RXR)) {
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		BCM283X_PRIV(dev)->count = bcm283x_spi0_do_transfer(dev,
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				BCM283X_PRIV(dev)->in, BCM283X_PRIV(dev)->out,
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					min(BCM283X_SPI0_RX_FIFO_HW, BCM283X_PRIV(dev)->count),
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					min(BCM283X_SPI0_RX_FIFO_HW, BCM283X_PRIV(dev)->count));
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		if (BCM283X_PRIV(dev)->received_data && BCM283X_PRIV(dev)->count > 0) {
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			BCM283X_PRIV(dev)->send_complete(dev, BCM283X_PRIV(dev)->count);
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		}
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	}
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	return ret;
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}
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static struct dma_ctrl_blk *bcm283x_init_dma_block_spi_in(struct spi_device *dev,
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		struct dma_mem_handle  *mem_handle, uint32_t offset, void *src, uint32_t bytes,
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		struct dma_ctrl_blk *next_conbk, bool int_enable) {
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	assert( (((uint32_t)(mem_handle->physical_addr) + offset) & ~MEM_ALGN_256 ) == ((uint32_t)(mem_handle->physical_addr) + offset));
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	struct dma_ctrl_blk *cbp = (struct dma_ctrl_blk *)(mem_handle->physical_addr + offset);
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	cbp->ti = DMA_TI_PERMAP(DMA_PERMAP_SPI_TX) | DMA_TI_SRC_INC | DMA_TI_DEST_DREQ | DMA_TI_WAIT_RESP;
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	cbp->dest_ad = (uint32_t)DMA_PERF_TO_BUS((uint32_t)&(REGS_SPI0->fifo));
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	cbp->stride = 0x0;
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	cbp->source_ad = (uint32_t)DMA_PHYS_TO_BUS((uint32_t)src);
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	cbp->txfr_len = bytes;
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	cbp->nextconbk = ( next_conbk == NULL ? 0x00 : (uint32_t)DMA_PHYS_TO_BUS((uint32_t)next_conbk) );
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	if(int_enable){
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		cbp->ti |= DMA_TI_INTEN;
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	}
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	else {
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		cbp->ti &= ~DMA_TI_INTEN;
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	}
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	return cbp;
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}
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static struct dma_ctrl_blk *bcm283x_init_dma_block_spi_out(struct spi_device *dev,
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		struct dma_mem_handle  *mem_handle, uint32_t offset, void *dest, uint32_t bytes,
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		struct dma_ctrl_blk *next_conbk, bool int_enable) {
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	assert( (((uint32_t)(mem_handle->physical_addr) + offset) & ~MEM_ALGN_256 ) == ((uint32_t)(mem_handle->physical_addr) + offset));
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	struct dma_ctrl_blk *cbp = (struct dma_ctrl_blk *)(mem_handle->physical_addr + offset);
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	cbp->ti = DMA_TI_PERMAP(DMA_PERMAP_SPI_RX) | DMA_TI_DEST_INC | DMA_TI_SRC_DREQ | DMA_TI_WAIT_RESP;
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	cbp->source_ad = (uint32_t)DMA_PERF_TO_BUS((uint32_t)&(REGS_SPI0->fifo));
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	cbp->stride = 0x0;
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	cbp->dest_ad = (uint32_t)DMA_PHYS_TO_BUS((uint32_t)dest);
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	cbp->txfr_len = bytes;
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	cbp->nextconbk = ( next_conbk == NULL ? 0x00 : (uint32_t)DMA_PHYS_TO_BUS((uint32_t)next_conbk) );
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	if(int_enable) {
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		cbp->ti |= DMA_TI_INTEN;
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	}
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	else {
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		cbp->ti &= ~DMA_TI_INTEN;
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	}
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	return cbp;
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}
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/*
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    // Hi 16 bits are length, lower 8 bits are the lower 8 bits of SPI control register
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 * 
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 * For SPI Device: txfr_len is in top sixteen bits and control register settings are in [7:0]
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 * (the bottom eight bits) for TA = 1, CS, CPOL, CPHA 
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*/
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static int bcm283x_spi0_transfer(struct spi_device *dev, uint8_t *inbuf, uint8_t *outbuf, int count) {
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    // Interrupt mode
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    if( ( (REGS_SPI0->cs & SPI0_CS_INTD) || (REGS_SPI0->cs & SPI0_CS_INTR) ) ) {
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        if(count < 0) {
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            // count < 0 is signal to trigger interrupt and return
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            BCM283X_PRIV(dev)->count = -1 * count;    /* set the target amount to output in series of interrupt transfers */
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            BCM283X_PRIV(dev)->in = inbuf;
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            BCM283X_PRIV(dev)->out = outbuf;
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            REGS_SPI0->dlen = DLEN_NO_DMA_VALUE;
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            REGS_SPI0->cs |= SPI0_CS_CLEAR( SPI0_tx_fifo | SPI0_rx_fifo ) | SPI0_CS_TA; // clear FIFO and Assert
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            return 0;
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        } else {
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            // called in interrupt handler to send/receive data
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            BCM283X_PRIV(dev)->count -= bcm283x_spi0_do_transfer(dev, inbuf, outbuf, min(BCM283X_SPI0_TX_FIFO_FL,count), BCM283X_SPI0_RX_FIFO_HW);
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            REGS_SPI0->cs &= ~SPI0_CS_TA; // De-assert
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            return 0;
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        }
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    }
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    // DMA Mode
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    if(REGS_SPI0->cs & SPI0_CS_DMAEN) { 
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        REGS_SPI0->dlen = count;    
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        // Receive - start dma transfer
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        dma_transfer_conbk(BCM283X_PRIV(dev)->dma_chan_out, (volatile struct dma_ctrl_blk *)outbuf);
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        // Transmit - start dma transfer
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        dma_transfer_conbk(BCM283X_PRIV(dev)->dma_chan_in, (volatile struct dma_ctrl_blk *)inbuf);
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        // Activate SPI
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        REGS_SPI0->cs |= SPI0_CS_ADCS | SPI0_CS_CLEAR( SPI0_tx_fifo | SPI0_rx_fifo ) | SPI0_CS_TA; // clear FIFO and Assert
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    } else { 
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        // Poll mode - bytes send, bytes receive
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        REGS_SPI0->cs |= SPI0_CS_CLEAR( SPI0_tx_fifo | SPI0_rx_fifo ) | SPI0_CS_TA; // clear FIFO and Assert
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        /* because we need to write all tx data before transfer competed. */
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        REGS_SPI0->dlen = DLEN_NO_DMA_VALUE;
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        bcm283x_spi0_do_transfer(dev, inbuf, outbuf, count, count);
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        REGS_SPI0->cs &= ~SPI0_CS_TA; // De-assert
370
    }
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    return 0;
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}
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struct spi_ops bcm283x_spi0_ops = {
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    .select   = bcm283x_spi0_select,
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    .transfer = bcm283x_spi0_transfer,
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};
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PERIPH_MEMORY_DEFINE(bcm283x_spi0, PBASE, sizeof(struct bcm283x_spi_regs));
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static struct bcm283x_spi_dev bcm283x_spi_dev = {
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		.regs = REGS_SPI0,
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		.init_dma_block_spi_in = bcm283x_init_dma_block_spi_in,
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		.init_dma_block_spi_out = bcm283x_init_dma_block_spi_out
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};
386

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SPI_DEV_DEF("spi0", &bcm283x_spi0_ops, &bcm283x_spi_dev, 0);
388

389
EMBOX_UNIT_INIT(bcm283x_spi0_init);
390