embox

pic32mx_uart.c
253 строки · 6.4 Кб
Перенос по словам
1
/**
2
 * @file
3
 * @brief
4
 *
5
 * @author  Anton Kozlov
6
 * @date    13.09.2012
7
 */
8

9

10
#include <hal/reg.h>
11
#include <embox/unit.h>
12

13
#include <drivers/diag.h>
14

15
#define UART_NM 5
16

17
#define BAUD_RATE 38400
18

19
#define PERPH_CLK (80 * 1000000)
20

21
#define U1ABRG 0xBF806040
22
#define U1ABRGCLR 0xBF806044
23
#define U1ABRGINV 0xBF80604C
24
#define U1ABRGSET 0xBF806048
25
#define U1AMODE 0xBF806000
26
#define U1AMODECLR 0xBF806004
27
#define U1AMODEINV 0xBF80600C
28
#define U1AMODESET 0xBF806008
29
#define U1ARXREG 0xBF806030
30
#define U1ASTA 0xBF806010
31
#define U1ASTACLR 0xBF806014
32
#define U1ASTAINV 0xBF80601C
33
#define U1ASTASET 0xBF806018
34
#define U1ATXREG 0xBF806020
35
#define U1BBRG 0xBF806240
36
#define U1BBRGCLR 0xBF806244
37
#define U1BBRGINV 0xBF80624C
38
#define U1BBRGSET 0xBF806248
39
#define U1BMODE 0xBF806200
40
#define U1BMODECLR 0xBF806204
41
#define U1BMODEINV 0xBF80620C
42
#define U1BMODESET 0xBF806208
43
#define U1BRG 0xBF806040
44
#define U1BRGCLR 0xBF806044
45
#define U1BRGINV 0xBF80604C
46
#define U1BRGSET 0xBF806048
47
#define U1BRXREG 0xBF806230
48
#define U1BSTA 0xBF806210
49
#define U1BSTACLR 0xBF806214
50
#define U1BSTAINV 0xBF80621C
51
#define U1BSTASET 0xBF806218
52
#define U1BTXREG 0xBF806220
53
#define U1MODE 0xBF806000
54
#define U1MODECLR 0xBF806004
55
#define U1MODEINV 0xBF80600C
56
#define U1MODESET 0xBF806008
57
#define U1RXREG 0xBF806030
58
#define U1STA 0xBF806010
59
#define U1STACLR 0xBF806014
60
#define U1STAINV 0xBF80601C
61
#define U1STASET 0xBF806018
62
#define U1TXREG 0xBF806020
63
#define U2ABRG 0xBF806440
64
#define U2ABRGCLR 0xBF806444
65
#define U2ABRGINV 0xBF80644C
66
#define U2ABRGSET 0xBF806448
67
#define U2AMODE 0xBF806400
68
#define U2AMODECLR 0xBF806404
69
#define U2AMODEINV 0xBF80640C
70
#define U2AMODESET 0xBF806408
71
#define U2ARXREG 0xBF806430
72
#define U2ASTA 0xBF806410
73
#define U2ASTACLR 0xBF806414
74
#define U2ASTAINV 0xBF80641C
75
#define U2ASTASET 0xBF806418
76
#define U2ATXREG 0xBF806420
77
#define U2BBRG 0xBF806640
78
#define U2BBRGCLR 0xBF806644
79
#define U2BBRGINV 0xBF80664C
80
#define U2BBRGSET 0xBF806648
81
#define U2BMODE 0xBF806600
82
#define U2BMODECLR 0xBF806604
83
#define U2BMODEINV 0xBF80660C
84
#define U2BMODESET 0xBF806608
85
#define U2BRG 0xBF806840
86
#define U2BRGCLR 0xBF806844
87
#define U2BRGINV 0xBF80684C
88
#define U2BRGSET 0xBF806848
89
#define U2BRXREG 0xBF806630
90
#define U2BSTA 0xBF806610
91
#define U2BSTACLR 0xBF806614
92
#define U2BSTAINV 0xBF80661C
93
#define U2BSTASET 0xBF806618
94
#define U2BTXREG 0xBF806620
95
#define U2MODE 0xBF806800
96
#define U2MODECLR 0xBF806804
97
#define U2MODEINV 0xBF80680C
98
#define U2MODESET 0xBF806808
99
#define U2RXREG 0xBF806830
100
#define U2STA 0xBF806810
101
#define U2STACLR 0xBF806814
102
#define U2STAINV 0xBF80681C
103
#define U2STASET 0xBF806818
104
#define U2TXREG 0xBF806820
105
#define U3ABRG 0xBF806840
106
#define U3ABRGCLR 0xBF806844
107
#define U3ABRGINV 0xBF80684C
108
#define U3ABRGSET 0xBF806848
109
#define U3AMODE 0xBF806800
110
#define U3AMODECLR 0xBF806804
111
#define U3AMODEINV 0xBF80680C
112
#define U3AMODESET 0xBF806808
113
#define U3ARXREG 0xBF806830
114
#define U3ASTA 0xBF806810
115
#define U3ASTACLR 0xBF806814
116
#define U3ASTAINV 0xBF80681C
117
#define U3ASTASET 0xBF806818
118
#define U3ATXREG 0xBF806820
119
#define U3BBRG 0xBF806A40
120
#define U3BBRGCLR 0xBF806A44
121
#define U3BBRGINV 0xBF806A4C
122
#define U3BBRGSET 0xBF806A48
123
#define U3BMODE 0xBF806A00
124
#define U3BMODECLR 0xBF806A04
125
#define U3BMODEINV 0xBF806A0C
126
#define U3BMODESET 0xBF806A08
127
#define U3BRG 0xBF806440
128
#define U3BRGCLR 0xBF806444
129
#define U3BRGINV 0xBF80644C
130
#define U3BRGSET 0xBF806448
131
#define U3BRXREG 0xBF806A30
132
#define U3BSTA 0xBF806A10
133
#define U3BSTACLR 0xBF806A14
134
#define U3BSTAINV 0xBF806A1C
135
#define U3BSTASET 0xBF806A18
136
#define U3BTXREG 0xBF806A20
137
#define U3MODE 0xBF806400
138
#define U3MODECLR 0xBF806404
139
#define U3MODEINV 0xBF80640C
140
#define U3MODESET 0xBF806408
141
#define U3RXREG 0xBF806430
142
#define U3STA 0xBF806410
143
#define U3STACLR 0xBF806414
144
#define U3STAINV 0xBF80641C
145
#define U3STASET 0xBF806418
146
#define U3TXREG 0xBF806420
147
#define U4BRG 0xBF806240
148
#define U4BRGCLR 0xBF806244
149
#define U4BRGINV 0xBF80624C
150
#define U4BRGSET 0xBF806248
151
#define U4MODE 0xBF806200
152
#define U4MODECLR 0xBF806204
153
#define U4MODEINV 0xBF80620C
154
#define U4MODESET 0xBF806208
155
#define U4RXREG 0xBF806230
156
#define U4STA 0xBF806210
157
#define U4STACLR 0xBF806214
158
#define U4STAINV 0xBF80621C
159
#define U4STASET 0xBF806218
160
#define U4TXREG 0xBF806220
161
#define U5BRG 0xBF806A40
162
#define U5BRGCLR 0xBF806A44
163
#define U5BRGINV 0xBF806A4C
164
#define U5BRGSET 0xBF806A48
165
#define U5MODE 0xBF806A00
166
#define U5MODECLR 0xBF806A04
167
#define U5MODEINV 0xBF806A0C
168
#define U5MODESET 0xBF806A08
169
#define U5RXREG 0xBF806A30
170
#define U5STA 0xBF806A10
171
#define U5STACLR 0xBF806A14
172
#define U5STAINV 0xBF806A1C
173
#define U5STASET 0xBF806A18
174
#define U5TXREG 0xBF806A20
175
#define U6BRG 0xBF806640
176
#define U6BRGCLR 0xBF806644
177
#define U6BRGINV 0xBF80664C
178
#define U6BRGSET 0xBF806648
179
#define U6MODE 0xBF806600
180
#define U6MODECLR 0xBF806604
181
#define U6MODEINV 0xBF80660C
182
#define U6MODESET 0xBF806608
183
#define U6RXREG 0xBF806630
184
#define U6STA 0xBF806610
185
#define U6STACLR 0xBF806614
186
#define U6STAINV 0xBF80661C
187
#define U6STASET 0xBF806618
188
#define U6TXREG 0xBF806620
189

190
#define __UxREG(uart_nmb, reg_nm) U ## uart_nmb ## reg_nm
191
#define _UxREG(uart_nmb, reg_nm) __UxREG(uart_nmb, reg_nm)
192
#define UxREG(reg_nm) _UxREG(UART_NM, reg_nm)
193

194
#define UxBRG	UxREG(BRG)   /* Baud rate generator */
195
#define UxMODE	UxREG(MODE)  /* Mode */
196
#define UxSTA	UxREG(STA)   /* Status */
197
#define UxRXREG UxREG(RXREG) /* Receive buffer */
198
#define UxTXREG UxREG(TXREG) /* Transmit buffer */
199

200
#define MODE_ON   0x8000     /* UART Enable */
201
#define MODE_RTSSMD (1 << 11)
202

203
#define STA_URXEN 0x1000     /* Receive enable */
204
#define STA_UTXEN 0x400	     /* Transmit enable */
205
#define STA_URXDA 0x1        /* Receive data avaible */
206
#define STA_UTXBF (1 << 9)      /* Transmit data full */
207
#define STA_UTRMT (1 << 8)
208

209
#define BRG_VAL (PERPH_CLK / (16 * BAUD_RATE) - 1)
210

211

212
extern void mips_delay(int cnt);
213

214
#define TRISB            0xBF886040
215
#define PORTB            0xBF886050
216

217
static char pic32_uart_diag_getc(const struct diag *diag) {
218
	return REG_LOAD(UxRXREG);
219
}
220

221
static void pic32_uart_diag_putc(const struct diag *diag, char c) {
222
	while (REG_LOAD(UxSTA) & STA_UTXBF) {
223

224
	}
225

226
	REG_STORE(UxTXREG, c);
227
}
228

229
static int pic32_uart_diag_kbhit(const struct diag *diag) {
230
	return REG_LOAD(UxSTA) & STA_URXDA;
231
}
232

233
static int pic32_uart_diag_init(const struct diag *diag) {
234
	REG_STORE(TRISB, 0);
235
	REG_STORE(PORTB, 0);
236

237
	REG_STORE(UxMODE, 0);
238
	REG_STORE(UxBRG,  BRG_VAL);
239

240
	REG_STORE(UxMODE, MODE_ON);
241
	REG_STORE(UxSTA,  STA_URXEN | STA_UTXEN);
242

243
	mips_delay(100000);
244

245
	return 0;
246
}
247

248
DIAG_OPS_DEF(
249
		.init = pic32_uart_diag_init,
250
		.putc = pic32_uart_diag_putc,
251
		.getc = pic32_uart_diag_getc,
252
		.kbhit = pic32_uart_diag_kbhit,
253
);
254
embox

Использование cookies
