embox
274 строки · 9.5 Кб
1/**
2* @file
3
4* @date 01 june 2024
5* @author: Anton Bondarev
6*/
7#include <stdint.h>8
9#include <drivers/serial/uart_dev.h>10#include <framework/mod/options.h>11#include <hal/reg.h>12
13#include <drivers/gpio/gpio.h>14#include <drivers/gpio/mikron_gpio.h>15
16#include <config/board_config.h>17
18#define SYSFREQ 32000000 /* 32MHz*/19#define USE_BOARD_CONF OPTION_GET(BOOLEAN, use_bconf)20
21#if USE_BOARD_CONF22#include "uart_setup_hw_board_config.inc"23#else24static inline int uart_setup_hw(struct uart *dev) {25gpio_setup_mode(GPIO_PORT_B, 1 << 8, GPIO_MODE_OUT_ALTERNATE | GPIO_ALTERNATE(0x1));26gpio_setup_mode(GPIO_PORT_B, 1 << 9, GPIO_MODE_OUT_ALTERNATE | GPIO_ALTERNATE(0x1));27return 0;28}
29#endif /* USE_BOARD_CONF */30
31#define UART_CONTROL1_M1_S 2832#define UART_CONTROL1_M1_M (1 << UART_CONTROL1_M1_S)33#define UART_CONTROL1_M0_S 1234#define UART_CONTROL1_M0_M (1 << UART_CONTROL1_M0_S)35#define UART_CONTROL1_M_8BIT_M (0)36#define UART_CONTROL1_M_9BIT_M (UART_CONTROL1_M0_M)37#define UART_CONTROL1_M_7BIT_M (UART_CONTROL1_M1_M)38#define UART_CONTROL1_M_M (UART_CONTROL1_M1_M | UART_CONTROL1_M0_M)39#define UART_CONTROL1_M(V) (((((v) / 10) << UART_CONTROL1_M1_S) | (((v) % 10) << UART_CONTROL1_M0_S)) & UART_CONTROL1_M_M)40#define UART_CONTROL1_PCE_S 1041#define UART_CONTROL1_PCE_M (1 << UART_CONTROL1_PCE_S)42#define UART_CONTROL1_PS_S 943#define UART_CONTROL1_PS_M (1 << UART_CONTROL1_PS_S)44#define UART_CONTROL1_PEIE_S 845#define UART_CONTROL1_PEIE_M (1 << UART_CONTROL1_PEIE_S)46#define UART_CONTROL1_TXEIE_S 747#define UART_CONTROL1_TXEIE_M (1 << UART_CONTROL1_TXEIE_S)48#define UART_CONTROL1_TCIE_S 649#define UART_CONTROL1_TCIE_M (1 << UART_CONTROL1_TCIE_S)50#define UART_CONTROL1_RXNEIE_S 551#define UART_CONTROL1_RXNEIE_M (1 << UART_CONTROL1_RXNEIE_S)52#define UART_CONTROL1_IDLEIE_S 453#define UART_CONTROL1_IDLEIE_M (1 << UART_CONTROL1_IDLEIE_S)54#define UART_CONTROL1_TE_S 355#define UART_CONTROL1_TE_M (1 << UART_CONTROL1_TE_S)56#define UART_CONTROL1_RE_S 257#define UART_CONTROL1_RE_M (1 << UART_CONTROL1_RE_S)58#define UART_CONTROL1_UE_S 059#define UART_CONTROL1_UE_M (1 << UART_CONTROL1_UE_S)60
61#define UART_CONTROL2_MSBFIRST_S 1962#define UART_CONTROL2_MSBFIRST_M (1 << UART_CONTROL2_MSBFIRST_S)63#define UART_CONTROL2_DATAINV_S 1864#define UART_CONTROL2_DATAINV_M (1 << UART_CONTROL2_DATAINV_S)65#define UART_CONTROL2_TXINV_S 1766#define UART_CONTROL2_TXINV_M (1 << UART_CONTROL2_TXINV_S)67#define UART_CONTROL2_RXINV_S 1668#define UART_CONTROL2_RXINV_M (1 << UART_CONTROL2_RXINV_S)69#define UART_CONTROL2_SWAP_S 1570#define UART_CONTROL2_SWAP_M (1 << UART_CONTROL2_SWAP_S)71#define UART_CONTROL2_LBM_S 1472#define UART_CONTROL2_LBM_M (1 << UART_CONTROL2_LBM_S)73#define UART_CONTROL2_STOP_1_S 1374#define UART_CONTROL2_STOP_1_M (1 << UART_CONTROL2_STOP_1_S)75#define UART_CONTROL2_CLKEN_S 1176#define UART_CONTROL2_CLKEN_M (1 << UART_CONTROL2_CLKEN_S)77#define UART_CONTROL2_CPOL_S 1078#define UART_CONTROL2_CPOL_M (1 << UART_CONTROL2_CPOL_S)79#define UART_CONTROL2_CPHA_S 980#define UART_CONTROL2_CPHA_M (1 << UART_CONTROL2_CPHA_S)81#define UART_CONTROL2_LBCL_S 882#define UART_CONTROL2_LBCL_M (1 << UART_CONTROL2_LBCL_S)83#define UART_CONTROL2_LBDIE_S 684#define UART_CONTROL2_LBDIE_M (1 << UART_CONTROL2_LBDIE_S)85
86#define UART_CONTROL3_OVRDIS_S 1287#define UART_CONTROL3_OVRDIS_M (1 << UART_CONTROL3_OVRDIS_S)88#define UART_CONTROL3_CTSIE_S 1089#define UART_CONTROL3_CTSIE_M (1 << UART_CONTROL3_CTSIE_S)90#define UART_CONTROL3_CTSE_S 991#define UART_CONTROL3_CTSE_M (1 << UART_CONTROL3_CTSE_S)92#define UART_CONTROL3_RTSE_S 893#define UART_CONTROL3_RTSE_M (1 << UART_CONTROL3_RTSE_S)94#define UART_CONTROL3_DMAT_S 795#define UART_CONTROL3_DMAT_M (1 << UART_CONTROL3_DMAT_S)96#define UART_CONTROL3_DMAR_S 697#define UART_CONTROL3_DMAR_M (1 << UART_CONTROL3_DMAR_S)98#define UART_CONTROL3_HDSEL_S 399#define UART_CONTROL3_HDSEL_M (1 << UART_CONTROL3_HDSEL_S)100#define UART_CONTROL3_BKRQ_S 2101#define UART_CONTROL3_BKRQ_M (1 << UART_CONTROL3_BKRQ_S)102// #define UART_CONTROL3_IREN_S 1
103// #define UART_CONTROL3_IREN_M (1 << UART_CONTROL3_IREN_S)
104#define UART_CONTROL3_EIE_S 0105#define UART_CONTROL3_EIE_M (1 << UART_CONTROL3_EIE_S)106
107#define UART_DIVIDER_BRR_S 0108#define UART_DIVIDER_BRR_M (0xFFFF << UART_DIVIDER_BRR_S)109
110#define UART_FLAGS_REACK_S 22111#define UART_FLAGS_REACK_M (1 << UART_FLAGS_REACK_S)112#define UART_FLAGS_TEACK_S 21113#define UART_FLAGS_TEACK_M (1 << UART_FLAGS_TEACK_S)114#define UART_FLAGS_BUSY_S 16115#define UART_FLAGS_BUSY_M (1 << UART_FLAGS_BUSY_S)116#define UART_FLAGS_CTS_S 10117#define UART_FLAGS_CTS_M (1 << UART_FLAGS_CTS_S)118#define UART_FLAGS_CTSIF_S 9119#define UART_FLAGS_CTSIF_M (1 << UART_FLAGS_CTSIF_S)120#define UART_FLAGS_LBDF_S 8121#define UART_FLAGS_LBDF_M (1 << UART_FLAGS_LBDF_S)122#define UART_FLAGS_TXE_S 7123#define UART_FLAGS_TXE_M (1 << UART_FLAGS_TXE_S)124#define UART_FLAGS_TC_S 6125#define UART_FLAGS_TC_M (1 << UART_FLAGS_TC_S)126#define UART_FLAGS_RXNE_S 5127#define UART_FLAGS_RXNE_M (1 << UART_FLAGS_RXNE_S)128#define UART_FLAGS_IDLE_S 4129#define UART_FLAGS_IDLE_M (1 << UART_FLAGS_IDLE_S)130#define UART_FLAGS_ORE_S 3131#define UART_FLAGS_ORE_M (1 << UART_FLAGS_ORE_S)132#define UART_FLAGS_NF_S 2133#define UART_FLAGS_NF_M (1 << UART_FLAGS_NF_S)134#define UART_FLAGS_FE_S 1135#define UART_FLAGS_FE_M (1 << UART_FLAGS_FE_S)136#define UART_FLAGS_PE_S 0137#define UART_FLAGS_PE_M (1 << UART_FLAGS_PE_S)138
139#define UART_MODEM_DTR_S 8140#define UART_MODEM_DTR_M (1 << UART_MODEM_DTR_S)141#define UART_MODEM_DCD_S 7142#define UART_MODEM_DCD_M (1 << UART_MODEM_DCD_S)143#define UART_MODEM_RI_S 6144#define UART_MODEM_RI_M (1 << UART_MODEM_RI_S)145#define UART_MODEM_DSR_S 5146#define UART_MODEM_DSR_M (1 << UART_MODEM_DSR_S)147#define UART_MODEM_DCDIF_S 3148#define UART_MODEM_DCDIF_M (1 << UART_MODEM_DCDIF_S)149#define UART_MODEM_RIIF_S 2150#define UART_MODEM_RIIF_M (1 << UART_MODEM_RIIF_S)151#define UART_MODEM_DSRIF_S 1152#define UART_MODEM_DSRIF_M (1 << UART_MODEM_DSRIF_S)153
154struct mikron_uart_regs {155volatile uint32_t CONTROL1;156volatile uint32_t CONTROL2;157volatile uint32_t CONTROL3;158volatile uint32_t DIVIDER;159volatile uint32_t _reserved0;160volatile uint32_t _reserved1;161volatile uint32_t _reserved2;162volatile uint32_t FLAGS;163volatile uint32_t _reserved3;164volatile uint32_t RXDATA;165volatile uint32_t TXDATA;166volatile uint32_t MODEM;167};168
169static void mikron_usart_set_baudrate(struct uart *dev) {170uint32_t divider = SYSFREQ / dev->params.baud_rate;171struct mikron_uart_regs *regs;172
173regs = (struct mikron_uart_regs *)(uintptr_t) dev->base_addr;174
175REG32_STORE(®s->DIVIDER, divider);176}
177
178static int mikron_usart_irq_enable(struct uart *dev,179const struct uart_params *params) {180struct mikron_uart_regs *regs;181
182regs = (struct mikron_uart_regs *)(uintptr_t) dev->base_addr;183
184if (params->uart_param_flags & UART_PARAM_FLAGS_USE_IRQ) {185REG32_ORIN(®s->CONTROL1, UART_CONTROL1_RXNEIE_M);186}187
188return 0;189}
190
191static int mikron_usart_irq_disable(struct uart *dev,192const struct uart_params *params) {193struct mikron_uart_regs *regs;194
195regs = (struct mikron_uart_regs *)(uintptr_t) dev->base_addr;196
197REG32_ANDIN(®s->CONTROL1, ~UART_CONTROL1_RXNEIE_M);198
199return 0;200}
201
202static int mikron_usart_setup(struct uart *dev,203const struct uart_params *params) {204uint32_t ctrl;205uint32_t flags;206struct mikron_uart_regs *regs;207
208regs = (struct mikron_uart_regs *)(uintptr_t) dev->base_addr;209
210ctrl = UART_CONTROL1_TE_M | UART_CONTROL1_RE_M | UART_CONTROL1_M_8BIT_M;211if (params->uart_param_flags & UART_PARAM_FLAGS_8BIT_WORD) {212ctrl |= UART_CONTROL1_M_8BIT_M;213}214ctrl |= UART_CONTROL1_UE_M;215
216/* Disable uart. */217REG32_STORE(®s->CONTROL1, 0);218REG32_STORE(®s->CONTROL2, 0);219REG32_STORE(®s->CONTROL3, 0);220REG32_STORE(®s->FLAGS, 0xFFFFFFFF);221
222uart_setup_hw(dev);223
224mikron_usart_set_baudrate(dev);225
226REG32_STORE(®s->CONTROL1, ctrl);227
228mikron_usart_irq_enable(dev, params);229
230flags = 0;231do {232flags = REG32_LOAD(®s->FLAGS);233} while(!(flags & UART_FLAGS_REACK_M) && !(flags | UART_FLAGS_TEACK_M));234
235return 0;236}
237
238static int mikron_usart_putc(struct uart *dev, int ch) {239struct mikron_uart_regs *regs;240
241regs = (struct mikron_uart_regs *)(uintptr_t) dev->base_addr;242
243while ( 0 == (REG_LOAD(®s->FLAGS) & UART_FLAGS_TXE_M)) {244}245
246REG32_STORE(®s->TXDATA, ch);247
248return 0;249}
250
251static int mikron_usart_has_symbol(struct uart *dev) {252struct mikron_uart_regs *regs;253
254regs = (struct mikron_uart_regs *)(uintptr_t) dev->base_addr;255
256return (REG_LOAD(®s->FLAGS) & UART_FLAGS_RXNE_M) ? 1 :0 ;257}
258
259static int mikron_usart_getc(struct uart *dev) {260struct mikron_uart_regs *regs;261
262regs = (struct mikron_uart_regs *)(uintptr_t) dev->base_addr;263
264return REG_LOAD(®s->RXDATA) & 0xFF;265}
266
267const struct uart_ops mikron_usart_ops = {268.uart_getc = mikron_usart_getc,269.uart_putc = mikron_usart_putc,270.uart_hasrx = mikron_usart_has_symbol,271.uart_setup = mikron_usart_setup,272.uart_irq_en = mikron_usart_irq_enable,273.uart_irq_dis = mikron_usart_irq_disable,274};275