embox

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/**
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 * @file
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 *
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 * @date 13.03.10
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 * @author Eldar Abusalimov
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 */
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#include <stdint.h>
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#include <errno.h>
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#include <drivers/common/memory.h>
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#include <drivers/amba_pnp.h>
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#include <hal/reg.h>
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#include <hal/system.h>
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#include <kernel/irq.h>
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#include <drivers/diag.h>
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#include <drivers/serial/uart_dev.h>
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#include <drivers/serial/diag_serial.h>
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#include <embox/unit.h>
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#include <kernel/printk.h>
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#define BAUD_RATE \
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	OPTION_GET(NUMBER, baud_rate)
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#define UART_SCALER_VAL \
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	(((SYS_CLOCK * 10) / (BAUD_RATE * 8) - 5) / 10)
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/* status register bit masks */
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#define UART_STAT_DR (1u << 0) /**< Data is available for read in RX register*/
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#define UART_STAT_TS (1u << 1) /**< TX shift register is empty */
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#define UART_STAT_TE (1u << 2) /**< TX FIFO is empty */
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#define UART_STAT_BR (1u << 3) /**< BREAK received */
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#define UART_STAT_OV (1u << 4) /**< 1 or more bytes lossed over overflow */
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#define UART_STAT_PE (1u << 5) /**< error in parity control */
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#define UART_STAT_FE (1u << 6) /**< error in frame */
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#define UART_STAT_TH (1u << 7) /**< TX FIFO is half-full */
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#define UART_STAT_RH (1u << 8) /**< RX FIFO is half-full */
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#define UART_STAT_TF (1u << 9) /**< TX FIFO is full */
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#define UART_STAT_RF (1u << 10)/**< RX FIFO is full */
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/* control register bit masks */
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#define UART_CTRL_RE (1u << 0)  /**< receiver enable */
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#define UART_CTRL_TE (1u << 1)  /**< transmitter enable */
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#define UART_CTRL_RI (1u << 2)  /**< interrupt after receiving frame */
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#define UART_CTRL_TI (1u << 3)  /**< interrupt after transmitting frame */
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#define UART_CTRL_PS (1u << 4)  /**< parity check (0 - oddness, 1 - evenness) */
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#define UART_CTRL_PE (1u << 5)  /**< parity control enable */
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#define UART_CTRL_FL (1u << 6)  /**< flow control with CTS/RTS enable (don't use) */
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#define UART_CTRL_LB (1u << 7)  /**< loopback enable */
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#define UART_CTRL_EC (1u << 8)  /**< external clock enable */
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#define UART_CTRL_TF (1u << 9)  /**< enable interrupt on FIFO transmitter layer */
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#define UART_CTRL_RF (1u << 10) /**< enable interrupt on FIFO receiver layer */
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#define UART_CTRL_DB (1u << 11) /**< debug mode enable (don't available) */
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#define UART_CTRL_OE (1u << 12) /**< output transmitter enable */
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#define UART_CTRL_FA (1u << 31) /**< set on when FIFO TX and RX are available */
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#define UART_DISABLE_ALL 0
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struct apbuart_regs {
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	/*------+------+
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	 | resv | data |
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	 | 31-8 | 7-0  |
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	 +------+------*/
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	/* 0x0 */uint32_t data;
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	/*-------+-------+-------+--+--+--+--+--+--+--+--+--+--+--+
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	 | RCNT  | TCNT  | resrv |RF|TF|RH|TH|FE|PE|OV|BR|TE|TS|DR|
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	 | 31-26 | 25-20 | 19-11 |10|9 |8 |7 |6 |5 |4 |3 |2 |1 |0 |
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	 +-------+-------+-------+--+--+--+--+--+--+--+--+--+--+--*/
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	/* 0x4 */uint32_t status;
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	/*--+-------+--+--+--+--+--+--+--+--+--+--+--+--+--+
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	 |FA| resrv |OE|DB|RF|TF|EC|LB|FL|PE|PS|TI|RI|TE|RE|
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	 |31| 30-13 |12|11|10|9 |8 |7 |6 |5 |4 |3 |2 |1 |0 |
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	 +--+-------+--+--+--+--+--+--+--+--+--+--+--+--+--*/
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	/* 0x8 */uint32_t ctrl;
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	/*-------+--------+
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	 | resrv | scaler |
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	 | 31-12 | 11-0   |
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	 +-------+--------*/
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	/* 0xC */uint32_t scaler;
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};
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static volatile struct apbuart_regs *dev_regs;
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static int dev_regs_init(void);
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EMBOX_UNIT_INIT(uart_init);
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static int apbuart_setup(struct uart *dev, const struct uart_params *params) {
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	int res;
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	if (NULL == dev_regs && 0 != (res = dev_regs_init())) {
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		return res;
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	}
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	assert(NULL != dev_regs);
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	REG_STORE(&dev_regs->ctrl, UART_DISABLE_ALL);
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	REG_STORE(&dev_regs->scaler, UART_SCALER_VAL);
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	if (params->uart_param_flags & UART_PARAM_FLAGS_USE_IRQ) {
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		REG_STORE(&dev_regs->ctrl, UART_CTRL_TE | UART_CTRL_RE | UART_CTRL_RI);
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	} else {
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		REG_STORE(&dev_regs->ctrl, UART_CTRL_TE | UART_CTRL_RE);
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	}
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	return 0;
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}
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static int apbuart_irq_en(struct uart *dev, const struct uart_params *params) {
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	if (params->uart_param_flags & UART_PARAM_FLAGS_USE_IRQ) {
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		REG_STORE(&dev_regs->ctrl, UART_CTRL_TE | UART_CTRL_RE | UART_CTRL_RI);
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	}
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	return 0;
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}
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static int apbuart_irq_dis(struct uart *dev, const struct uart_params *params) {
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	if (params->uart_param_flags & UART_PARAM_FLAGS_USE_IRQ) {
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		REG_STORE(&dev_regs->ctrl, UART_CTRL_TE | UART_CTRL_RE);
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	}
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	return 0;
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}
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static int apbuart_putc(struct uart *dev, int ch) {
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	while (!(UART_STAT_TE & REG_LOAD(&dev_regs->status))) {
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	}
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	REG_STORE(&dev_regs->data, (uint32_t) ch);
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	return 0;
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}
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static int apbuart_has_symbol(struct uart *dev) {
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	return (UART_STAT_DR & REG_LOAD(&dev_regs->status));
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}
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static int apbuart_getc(struct uart *dev) {
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	return REG_LOAD(&dev_regs->data);
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}
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#ifdef DRIVER_AMBAPP
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static int dev_regs_init() {
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	amba_dev_t amba_dev;
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	if (-1 == capture_amba_dev(&amba_dev, AMBAPP_VENDOR_GAISLER,
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					AMBAPP_DEVICE_GAISLER_APBUART, false, false)) {
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		printk("can't capture apb dev venID=0x%X, devID=0x%X\n",
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				AMBAPP_VENDOR_GAISLER, AMBAPP_DEVICE_GAISLER_APBUART);
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		return -ENODEV;
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	}
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	dev_regs = (volatile struct apbuart_regs *) amba_dev.bar[0].start;
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	return 0;
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}
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#elif OPTION_DEFINED(NUMBER,apbuart_base)
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PERIPH_MEMORY_DEFINE(apbuart, OPTION_GET(NUMBER,apbuart_base), sizeof(struct apbuart_regs));
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static int dev_regs_init() {
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	dev_regs = (volatile struct apbuart_regs *) OPTION_GET(NUMBER,apbuart_base);
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	return 0;
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}
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#else
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# error "Either DRIVER_AMBAPP or apbuart_base option must be defined"
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#endif /* DRIVER_AMBAPP */
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static const struct uart_ops uart_ops = {
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		.uart_getc = apbuart_getc,
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		.uart_putc = apbuart_putc,
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		.uart_hasrx = apbuart_has_symbol,
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		.uart_setup = apbuart_setup,
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		.uart_irq_en = apbuart_irq_en,
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		.uart_irq_dis = apbuart_irq_dis,
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};
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static struct uart uart0 = {
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		.irq_num = OPTION_GET(NUMBER,irq_num),
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		.base_addr = OPTION_GET(NUMBER,apbuart_base),
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		.uart_ops = &uart_ops,
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};
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static const struct uart_params uart_defparams = {
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		.baud_rate = OPTION_GET(NUMBER,baud_rate),
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		.uart_param_flags = UART_PARAM_FLAGS_8BIT_WORD | UART_PARAM_FLAGS_USE_IRQ,
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};
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static const struct uart_params uart_diag_params = {
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		.baud_rate = OPTION_GET(NUMBER,baud_rate),
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		.uart_param_flags = UART_PARAM_FLAGS_8BIT_WORD,
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};
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DIAG_SERIAL_DEF(&uart0, &uart_diag_params);
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static int uart_init(void) {
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	return uart_register(&uart0, &uart_defparams);
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}
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