embox

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/**
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 * @file
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 * @brief ARM PrimeCell Real Time Clock driver
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 * @author Denis Deryugin <deryugin.denis@gmail.com>
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 * @version 0.1
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 * @date 2019-07-18
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 */
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#include <time.h>
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#include <drivers/common/memory.h>
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#include <hal/reg.h>
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#include <kernel/irq.h>
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#include <drivers/rtc.h>
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#include <framework/mod/options.h>
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#include <embox/unit.h>
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EMBOX_UNIT_INIT(pl031_init);
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#define PL031_BASE      OPTION_GET(NUMBER, base_addr)
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#define PL031_IRQ       OPTION_GET(NUMBER, irq_nr)
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#define PL031_TARGET_HZ 1
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#define PL031_DR   (PL031_BASE + 0x00) /* Data register */
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#define PL031_MR   (PL031_BASE + 0x04) /* Match register */ 
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#define PL031_LR   (PL031_BASE + 0x08) /* Load register */
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#define PL031_CR   (PL031_BASE + 0x0C) /* Control register */
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#define PL031_IMSC (PL031_BASE + 0x10) /* Interrupt Mask Set or Clear register */
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#define PL031_RIS  (PL031_BASE + 0x14) /* Raw Interrupt Status register */
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#define PL031_MIS  (PL031_BASE + 0x18) /* Masked Interrupt Status register */
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#define PL031_ICR  (PL031_BASE + 0x1C) /* Interrupt Clear register */
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#define PL031_CR_START     (1 << 0)
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#define PL031_IMSC_EN      (1 << 0)
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#define PL031_ICR_CLEAR    (1 << 0)
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static irq_return_t pl031_irq_handler(unsigned int irq_nr, void *data) {
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	REG32_STORE(PL031_ICR, PL031_ICR_CLEAR); /* Clear interrupt */
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	rtc_update_irq(data, 1, (RTC_AF | RTC_IRQF));
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	return IRQ_HANDLED;
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}
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static int pl031_get_time(struct rtc_device *dev, struct tm *tm) {
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	time_t time;
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	time = REG32_LOAD(PL031_DR);
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	gmtime_r(&time, tm);
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	return 0;
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}
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static int pl031_set_time(struct rtc_device *dev, struct tm *tm) {
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	REG32_STORE(PL031_LR, mktime(tm));
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	return 0;
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}
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static int pl031_get_alarm(struct rtc_device *dev, struct tm *tm) {
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	time_t time;
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	time = REG32_LOAD(PL031_MR);
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	gmtime_r(&time, tm);
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	return 0;
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}
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static int pl031_set_alarm(struct rtc_device *dev, struct tm *tm) {
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	REG32_STORE(PL031_MR, mktime(tm));
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	return 0;
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}
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int pl031_alarm_irq_enable(struct rtc_device *dev, int enabled) {
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	if (enabled) {
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		REG32_STORE(PL031_IMSC, PL031_IMSC_EN); /* Enable IRQ */
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	} else {
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		REG32_STORE(PL031_IMSC, 0); /* disable IRQ */
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	}
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	return 0;
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}
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static struct rtc_ops pl031_ops = {
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	.get_time = pl031_get_time,
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	.set_time = pl031_set_time,
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	.get_alarm = pl031_get_alarm,
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	.set_alarm = pl031_set_alarm,
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	.alarm_irq_enable = pl031_alarm_irq_enable
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};
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static struct rtc_device pl031_rtc_device = {
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	.rtc_ops = &pl031_ops
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};
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RTC_DEVICE_DEF(&pl031_rtc_device);
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static int pl031_init(void) {
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	REG32_STORE(PL031_CR, PL031_CR_START);  /* Enable counter */
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	return irq_attach(PL031_IRQ,
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			pl031_irq_handler,
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			0,
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			&pl031_rtc_device,
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			"PL031");
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}
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STATIC_IRQ_ATTACH(PL031_IRQ, pl031_irq_handler, &pl031_rtc_device;);
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PERIPH_MEMORY_DEFINE(pl031, PL031_BASE, 0x20);
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