embox
1/**
2* @file
3* @brief
4*
5* @author Anton Kozlov
6* @date 07.08.2014
7*/
8
9#include <util/log.h>10
11#include <drivers/net/stm32cube_eth.h>12
13/*****************************************************************************
14Ethernet MSP Routines
15*****************************************************************************/
16/**
17* @brief Initializes the ETH MSP.
18* @param heth: ETH handle
19* @retval None
20*/
21void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) {22GPIO_InitTypeDef GPIO_InitStructure;23
24/* Ethernet pins configuration *****************************************/25/* STM32F764i-disco & STM32F746G-disco */26/*27RMII_REF_CLK ----------------------> PA1
28RMII_MDIO -------------------------> PA2
29RMII_MDC --------------------------> PC1
30RMII_MII_CRS_DV -------------------> PA7
31RMII_MII_RXD0 ---------------------> PC4
32RMII_MII_RXD1 ---------------------> PC5
33RMII_MII_RXER ---------------------> PG2
34RMII_MII_TX_EN --------------------> PG11
35RMII_MII_TXD0 ---------------------> PG13
36RMII_MII_TXD1 ---------------------> PG14
37*/
38
39/* Ethernet pins configuration ************************************************/40/* nucleo-f767zi */41/*42RMII_REF_CLK ----------------------> PA1
43RMII_MDIO -------------------------> PA2
44RMII_MDC --------------------------> PC1
45RMII_MII_CRS_DV -------------------> PA7
46RMII_MII_RXD0 ---------------------> PC4
47RMII_MII_RXD1 ---------------------> PC5
48RMII_MII_RXER ---------------------> PG2
49RMII_MII_TX_EN --------------------> PG11
50RMII_MII_TXD0 ---------------------> PG13
51RMII_MII_TXD1 ---------------------> PB13
52*/
53
54GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;55GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;56GPIO_InitStructure.Pull = GPIO_NOPULL;57GPIO_InitStructure.Alternate = GPIO_AF11_ETH;58
59/* Configure PA1, PA2 and PA7 */60__HAL_RCC_GPIOA_CLK_ENABLE();61GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;62HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);63
64#if defined(STM32F767xx) && defined(USE_STM32F7XX_NUCLEO_144)65/* Configure PB13 */66__HAL_RCC_GPIOB_CLK_ENABLE();67GPIO_InitStructure.Pin = GPIO_PIN_13;68HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);69#endif70
71/* Configure PC1, PC4 and PC5 */72__HAL_RCC_GPIOC_CLK_ENABLE();73GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;74HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);75
76/* Configure PG2, PG11, PG13 and PG14 */77__HAL_RCC_GPIOG_CLK_ENABLE();78#if !defined(USE_STM32F7XX_NUCLEO_144)79/* Configure PG2, PG11, PG13 and PG14 */80GPIO_InitStructure.Pin =81GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;82#else83GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;84#endif85HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);86
87/* Enable ETHERNET clock */88__HAL_RCC_ETH_CLK_ENABLE();89
90#if defined(STM32F767xx) && defined(USE_STM32F7XX_NUCLEO_144)91/* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */92HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_PLLCLK, RCC_MCODIV_4);93#endif94
95}
96