embox

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/**
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 * @file
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 * @brief
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 *
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 * @author  Anton Kozlov
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 * @date    07.08.2014
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 */
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#include <util/log.h>
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#include <errno.h>
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#include <string.h>
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#include <stdio.h>
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#include <util/math.h>
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#include <kernel/irq.h>
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#include <hal/reg.h>
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#include <net/netdevice.h>
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#include <net/inetdevice.h>
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#include <net/l0/net_entry.h>
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#include <net/l2/ethernet.h>
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#include <net/l3/arp.h>
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#include <net/util/show_packet.h>
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#include <drivers/net/stm32cube_eth.h>
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#include <embox/unit.h>
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#include <arm/cpu_cache.h>
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EMBOX_UNIT_INIT(stm32eth_init);
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#define ETH_DMA_TRANSMIT_TIMEOUT                (20U)
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#define STM32ETH_IRQ   OPTION_GET(NUMBER, irq)
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#define USE_RMII       OPTION_GET(NUMBER, use_rmii)
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static ETH_HandleTypeDef stm32_eth_handler;
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static ETH_TxPacketConfig TxConfig;
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static ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] \
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	__attribute__ ((aligned (4))) SRAM_DEVICE_MEM_SECTION;
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static uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] \
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	 __attribute__ ((aligned (4))) SRAM_NOCACHE_SECTION;
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#if ETH_TXBUFNB == 0
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#undef  ETH_TXBUFNB
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#define ETH_TXBUFNB 4
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#define TX_NO_BUFF  1
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#endif
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#ifdef TX_NO_BUFF
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static ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] \
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	__attribute__ ((aligned (4))) SRAM_DEVICE_MEM_SECTION;
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#else /* TX_NO_BUFF */
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static uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] \
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	__attribute__ ((aligned (4))) SRAM_NOCACHE_SECTION;
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static ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] \
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	__attribute__ ((aligned (4))) SRAM_DEVICE_MEM_SECTION;
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#endif /* TX_NO_BUFF */
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static void low_level_init(unsigned char mac[6]) {
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	memset(&stm32_eth_handler, 0, sizeof(stm32_eth_handler));
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	stm32_eth_handler.Instance = (ETH_TypeDef *) ETH_BASE;
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	/* Fill ETH_InitStructure parametrs */
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	stm32_eth_handler.Init.MACAddr = mac;
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#if USE_RMII
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	stm32_eth_handler.Init.MediaInterface = HAL_ETH_RMII_MODE;
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#else
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	stm32_eth_handler.Init.MediaInterface = HAL_ETH_MII_MODE;
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#endif
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	stm32_eth_handler.Init.RxDesc = DMARxDscrTab;
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	stm32_eth_handler.Init.TxDesc = DMATxDscrTab;
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	stm32_eth_handler.Init.RxBuffLen = ETH_TX_BUF_SIZE;
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	if (HAL_OK != HAL_ETH_Init(&stm32_eth_handler)) {
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		log_error("HAL_ETH_Init error\n");
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	}
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	if (stm32_eth_handler.gState == HAL_ETH_STATE_READY) {
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	}
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	for (int idx = 0; idx < ETH_RX_DESC_CNT; idx ++)
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	{
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		HAL_ETH_DescAssignMemory(&stm32_eth_handler, idx, Rx_Buff[idx], NULL);
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	}
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	/* Set Tx packet config common parameters */
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	memset(&TxConfig, 0, sizeof(ETH_TxPacketConfig));
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	TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
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	TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
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	TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
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	ETH_MACConfigTypeDef MACConf;
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	/* Get MAC Config MAC */
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	HAL_ETH_GetMACConfig(&stm32_eth_handler, &MACConf);
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	MACConf.DuplexMode = ETH_FULLDUPLEX_MODE;
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	MACConf.Speed = ETH_SPEED_100M;
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	HAL_ETH_SetMACConfig(&stm32_eth_handler, &MACConf);
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	/* (#)Enable MAC and DMA transmission and reception: */
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	HAL_ETH_Start_IT(&stm32_eth_handler);
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}
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static uint8_t *low_level_input(int *len) {
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	uint8_t *buffer;
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	ETH_BufferTypeDef RxBuff;
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	uint32_t framelength = 0;
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	if (!HAL_ETH_IsRxDataAvailable(&stm32_eth_handler)) {
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		return NULL;
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	}
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	HAL_ETH_GetRxDataBuffer(&stm32_eth_handler, &RxBuff);
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	HAL_ETH_GetRxDataLength(&stm32_eth_handler, &framelength);
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	/* Build Rx descriptor to be ready for next data reception */
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	HAL_ETH_BuildRxDescriptors(&stm32_eth_handler);
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	/* Invalidate data cache for ETH Rx Buffers */
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	//SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, framelength);
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	buffer = RxBuff.buffer;
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	*len = framelength;
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	return buffer;
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}
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static int stm32eth_xmit(struct net_device *dev, struct sk_buff *skb);
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static int stm32eth_open(struct net_device *dev);
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static int stm32eth_set_mac(struct net_device *dev, const void *addr);
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static const struct net_driver stm32eth_ops = {
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		.xmit = stm32eth_xmit,
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		.start = stm32eth_open,
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		.set_macaddr = stm32eth_set_mac,
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};
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static int stm32eth_open(struct net_device *dev) {
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	low_level_init(dev->dev_addr);
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	return 0;
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}
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static int stm32eth_set_mac(struct net_device *dev, const void *addr) {
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	ETH_TypeDef *regs = (ETH_TypeDef *) ETH_BASE;
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	memcpy(dev->dev_addr, addr, ETH_ALEN);
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	regs->MACA0HR = ((uint32_t) dev->dev_addr[5] << 8) |
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	                ((uint32_t) dev->dev_addr[4] << 0);
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	regs->MACA0LR = ((uint32_t) dev->dev_addr[3] << 24) |
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	                ((uint32_t) dev->dev_addr[2] << 16) |
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	                ((uint32_t) dev->dev_addr[1] << 8)  |
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	                ((uint32_t) dev->dev_addr[0] << 0);
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	return ENOERR;
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}
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#ifdef TX_NO_BUFF
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static uint8_t Tx_Buff[ETH_TX_BUF_SIZE] \
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	__attribute__ ((aligned (4))) SRAM_NOCACHE_SECTION;
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static int stm32eth_xmit(struct net_device *dev, struct sk_buff *skb) {
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	ETH_BufferTypeDef Txbuffer;
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	show_packet(skb->mac.raw, skb->len, "tx");
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	memcpy((void *)Tx_Buff, skb->mac.raw, skb->len);
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	memset(&Txbuffer, 0, sizeof(Txbuffer));
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	Txbuffer.buffer = Tx_Buff;
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	Txbuffer.len = skb->len;
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	TxConfig.Length = skb->len;
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	TxConfig.TxBuffer = &Txbuffer;
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	HAL_ETH_Transmit(&stm32_eth_handler, &TxConfig, ETH_DMA_TRANSMIT_TIMEOUT);
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	skb_free(skb);
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	return 0;
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}
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#else
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static int stm32eth_xmit(struct net_device *dev, struct sk_buff *skb) {
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	__IO ETH_DMADescTypeDef *dma_tx_desc;
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	dma_tx_desc = stm32_eth_handler.TxDesc;
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	memcpy((void *)dma_tx_desc->Buffer1Addr, skb->mac.raw, skb->len);
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	/* Prepare transmit descriptors to give to DMA */
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	if (0 != HAL_ETH_TransmitFrame(&stm32_eth_handler, skb->len)) {
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		log_error("HAL_ETH_TransmitFrame failed\n");
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		return -1;
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	}
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	skb_free(skb);
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	return 0;
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}
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#endif
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static irq_return_t stm32eth_interrupt(unsigned int irq_num, void *dev_id) {
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	struct net_device *nic_p = dev_id;
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	struct sk_buff *skb;
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	ETH_HandleTypeDef *heth = &stm32_eth_handler;
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	if (!nic_p) {
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		return IRQ_NONE;
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	}
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	/* Packet received */
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	if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
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	{
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		if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
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		{
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			uint8_t *buffer;
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			int len;
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			/* Receive complete callback */
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			while (NULL != (buffer = low_level_input(&len))) {
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				/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
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				skb = skb_alloc(len);
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				if (!skb) {
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					log_error("skb_alloc failed\n");
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					continue;
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				}
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				/* copy received frame to pbuf chain */
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				memcpy(skb->mac.raw, buffer, len);
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				skb->dev = nic_p;
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				show_packet(skb->mac.raw, skb->len, "rx");
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				netif_rx(skb);
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			}
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			/* Clear the Eth DMA Rx IT pending bits */
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			__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
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		}
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	}
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	return IRQ_HANDLED;
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}
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static struct net_device *stm32eth_netdev;
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static int stm32eth_init(void) {
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	int res;
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	struct net_device *nic;
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	nic = (struct net_device *) etherdev_alloc(0);
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	if (nic == NULL) {
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		return -ENOMEM;
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	}
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	nic->drv_ops = &stm32eth_ops;
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	nic->irq = STM32ETH_IRQ;
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	nic->base_addr = ETH_BASE;
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	stm32eth_netdev = nic;
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	res = irq_attach(nic->irq, stm32eth_interrupt, 0, stm32eth_netdev, "");
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	if (res < 0) {
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		return res;
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	}
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	return inetdev_register_dev(nic);
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}
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STATIC_IRQ_ATTACH(STM32ETH_IRQ, stm32eth_interrupt, stm32eth_netdev);
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