embox

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/**
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 * @file
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 * @brief
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 *
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 * @author  Anton Kozlov
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 * @date    07.08.2014
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 */
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#include <errno.h>
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#include <string.h>
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#include <stdio.h>
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#include <util/math.h>
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#include <kernel/irq.h>
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#include <hal/reg.h>
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#include <net/netdevice.h>
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#include <net/inetdevice.h>
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#include <net/l0/net_entry.h>
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#include <net/l2/ethernet.h>
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#include <net/l3/arp.h>
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#include <net/util/show_packet.h>
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#include <drivers/net/stm32cube_eth.h>
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#include <util/log.h>
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#include <embox/unit.h>
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#include <arm/cpu_cache.h>
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EMBOX_UNIT_INIT(stm32eth_init);
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#define STM32ETH_IRQ   OPTION_GET(NUMBER, irq)
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static ETH_HandleTypeDef stm32_eth_handler;
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static ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] \
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	__attribute__ ((aligned (4))) SRAM_DEVICE_MEM_SECTION;
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static uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] \
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	 __attribute__ ((aligned (4))) SRAM_NOCACHE_SECTION;
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#if ETH_TXBUFNB == 0
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#undef  ETH_TXBUFNB
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#define ETH_TXBUFNB 4
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#define TX_NO_BUFF  1
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#endif
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#ifdef TX_NO_BUFF
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#undef TX_NO_BUFF
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#define TX_NO_BUFF  0
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#else /* TX_NO_BUFF */
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static uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] \
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	__attribute__ ((aligned (4))) SRAM_NOCACHE_SECTION;
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#endif /* TX_NO_BUFF */
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static ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] \
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	__attribute__ ((aligned (4))) SRAM_DEVICE_MEM_SECTION;
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static void low_level_init(unsigned char mac[6]) {
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	memset(&stm32_eth_handler, 0, sizeof(stm32_eth_handler));
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	stm32_eth_handler.Instance = (ETH_TypeDef *) ETH_BASE;
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	/* Fill ETH_InitStructure parametrs */
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	stm32_eth_handler.Init.MACAddr = mac;
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	stm32_eth_handler.Init.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE;
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	stm32_eth_handler.Init.Speed = ETH_SPEED_100M;
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	stm32_eth_handler.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
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	stm32_eth_handler.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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	stm32_eth_handler.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
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	stm32_eth_handler.Init.PhyAddress = PHY_ADDRESS;
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	stm32_eth_handler.Init.RxMode = ETH_RXINTERRUPT_MODE;
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	if (HAL_OK != HAL_ETH_Init(&stm32_eth_handler)) {
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		log_error("HAL_ETH_Init error\n");
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	}
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	if (stm32_eth_handler.State == HAL_ETH_STATE_READY) {
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		log_info("STATE_READY sp %d duplex %d\n",
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			stm32_eth_handler.Init.Speed, stm32_eth_handler.Init.DuplexMode);
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	}
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	/*(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:*/
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	HAL_ETH_DMATxDescListInit(&stm32_eth_handler, DMATxDscrTab, &Tx_Buff[0][0],
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			ETH_TXBUFNB); /*for Transmission process*/
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	if (HAL_OK != HAL_ETH_DMARxDescListInit(&stm32_eth_handler,
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			DMARxDscrTab, &Rx_Buff[0][0],
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			ETH_RXBUFNB)) { /*for Reception process*/
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		log_error("HAL_ETH_DMARxDescListInit error\n");
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	}
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	/* (#)Enable MAC and DMA transmission and reception: */
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	HAL_ETH_Start(&stm32_eth_handler);
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}
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static struct sk_buff *low_level_input(void) {
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	struct sk_buff *skb;
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	int len;
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	uint8_t *buffer;
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	/* get received frame */
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	if (HAL_ETH_GetReceivedFrame_IT(&stm32_eth_handler) != HAL_OK) {
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		return NULL;
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	}
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	/* Obtain the size of the packet and put it into the "len" variable. */
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	len = stm32_eth_handler.RxFrameInfos.length;
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	buffer = (uint8_t *) stm32_eth_handler.RxFrameInfos.buffer;
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	skb = NULL;
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	/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
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	skb = skb_alloc(len);
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	/* copy received frame to pbuf chain */
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	if (skb != NULL) {
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		memcpy(skb->mac.raw, buffer, len);
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	} else {
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		log_error("skb_alloc failed\n");
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	}
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	{
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		uint32_t i = 0;
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		__IO ETH_DMADescTypeDef *dmarxdesc;
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		/* Release descriptors to DMA */
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		dmarxdesc = stm32_eth_handler.RxFrameInfos.FSRxDesc;
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		/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
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		for (i = 0; i < stm32_eth_handler.RxFrameInfos.SegCount; i++) {
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			dmarxdesc->Status |= ETH_DMARXDESC_OWN;
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			dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
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		}
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		/* Clear Segment_Count */
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		stm32_eth_handler.RxFrameInfos.SegCount = 0;
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		/* When Rx Buffer unavailable flag is set: clear it and resume reception */
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		if ((stm32_eth_handler.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) {
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			/* Clear RBUS ETHERNET DMA flag */
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			stm32_eth_handler.Instance->DMASR = ETH_DMASR_RBUS;
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			/* Resume DMA reception */
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			stm32_eth_handler.Instance->DMARPDR = 0;
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		}
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	}
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	return skb;
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}
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static int stm32eth_xmit(struct net_device *dev, struct sk_buff *skb);
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static int stm32eth_open(struct net_device *dev);
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static int stm32eth_set_mac(struct net_device *dev, const void *addr);
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static const struct net_driver stm32eth_ops = {
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		.xmit = stm32eth_xmit,
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		.start = stm32eth_open,
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		.set_macaddr = stm32eth_set_mac,
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};
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static int stm32eth_open(struct net_device *dev) {
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	low_level_init(dev->dev_addr);
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	return 0;
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}
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static int stm32eth_set_mac(struct net_device *dev, const void *addr) {
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	ETH_TypeDef *regs = (ETH_TypeDef *) ETH_BASE;
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	memcpy(dev->dev_addr, addr, ETH_ALEN);
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	regs->MACA0HR = ((uint32_t) dev->dev_addr[5] << 8) |
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	                ((uint32_t) dev->dev_addr[4] << 0);
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	regs->MACA0LR = ((uint32_t) dev->dev_addr[3] << 24) |
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	                ((uint32_t) dev->dev_addr[2] << 16) |
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	                ((uint32_t) dev->dev_addr[1] << 8)  |
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	                ((uint32_t) dev->dev_addr[0] << 0);
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	return ENOERR;
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}
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#if defined (TX_NO_BUFF) && TX_NO_BUFF == 0
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static int stm32eth_xmit(struct net_device *dev, struct sk_buff *skb) {
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	__IO ETH_DMADescTypeDef *dma_tx_desc;
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	dma_tx_desc = stm32_eth_handler.TxDesc;
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	/* Transmit skbuff directly without any buffer. */
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	dma_tx_desc->Buffer1Addr = (uint32_t) skb->mac.raw;
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	/* Prepare transmit descriptors to give to DMA */
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	if (0 != HAL_ETH_TransmitFrame(&stm32_eth_handler, skb->len)) {
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		log_error("HAL_ETH_TransmitFrame failed\n");
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		return -1;
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	}
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	/* Wait until packet transmitted and descriptor released. */
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	while (dma_tx_desc->Status & ETH_DMATXDESC_OWN)
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		;
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	skb_free(skb);
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	return 0;
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}
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#else
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static int stm32eth_xmit(struct net_device *dev, struct sk_buff *skb) {
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	__IO ETH_DMADescTypeDef *dma_tx_desc;
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	dma_tx_desc = stm32_eth_handler.TxDesc;
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	memcpy((void *)dma_tx_desc->Buffer1Addr, skb->mac.raw, skb->len);
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	/* Prepare transmit descriptors to give to DMA */
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	if (0 != HAL_ETH_TransmitFrame(&stm32_eth_handler, skb->len)) {
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		log_error("HAL_ETH_TransmitFrame failed\n");
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		return -1;
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	}
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	skb_free(skb);
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	return 0;
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}
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#endif
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static irq_return_t stm32eth_interrupt(unsigned int irq_num, void *dev_id) {
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	struct net_device *nic_p = dev_id;
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	struct sk_buff *skb;
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	ETH_HandleTypeDef *heth = &stm32_eth_handler;
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	if (!nic_p) {
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		return IRQ_NONE;
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	}
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	if (heth->Instance->DMASR & ETH_DMA_FLAG_FBE) {
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		log_error("DMA error: DMASR = 0x%08x\n", heth->Instance->DMASR);
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	}
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	/* Frame received */
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	if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) {
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		/* Receive complete callback */
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		while (NULL != (skb = low_level_input())) {
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			skb->dev = nic_p;
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			show_packet(skb->mac.raw, skb->len, "rx");
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			netif_rx(skb);
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		}
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		/* Clear the Eth DMA Rx IT pending bits */
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		__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
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	}
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	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
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	return IRQ_HANDLED;
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}
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static struct net_device *stm32eth_netdev;
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static int stm32eth_init(void) {
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	int res;
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	struct net_device *nic;
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	nic = (struct net_device *) etherdev_alloc(0);
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	if (nic == NULL) {
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		return -ENOMEM;
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	}
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	nic->drv_ops = &stm32eth_ops;
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	nic->irq = STM32ETH_IRQ;
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	nic->base_addr = ETH_BASE;
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	stm32eth_netdev = nic;
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	res = irq_attach(nic->irq, stm32eth_interrupt, 0, stm32eth_netdev, "");
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	if (res < 0) {
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		return res;
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	}
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	return inetdev_register_dev(nic);
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}
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STATIC_IRQ_ATTACH(STM32ETH_IRQ, stm32eth_interrupt, stm32eth_netdev);
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