embox

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/**
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 * @file
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 *
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 * @date 10.05.2016
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 * @author: Anton Bondarev
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 */
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#include <errno.h>
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#include <stdint.h>
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#include <util/log.h>
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#include <kernel/irq.h>
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#include <net/skbuff.h>
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#include <net/netdevice.h>
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#include <net/l0/net_entry.h>
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#include <net/l2/ethernet.h>
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#include <net/inetdevice.h>
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#include <net/util/show_packet.h>
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#include <asm/io.h>
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#include <embox/unit.h>
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EMBOX_UNIT_INIT(mipsnet_init);
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#define BASE_ADDR    OPTION_GET(NUMBER,base_addr)
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#define IRQ_NUM      OPTION_GET(NUMBER,irq_num)
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/*
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 * Net status/control block as seen by sw in the core.
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 */
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struct mipsnet_regs {
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	/*
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	 * Device info for probing, reads as MIPSNET%d where %d is some
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	 * form of version.
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	 */
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	uint64_t devId;              /*0x00 */
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	/*
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	 * read only busy flag.
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	 * Set and cleared by the Net Device to indicate that an rx or a tx
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	 * is in progress.
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	 */
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	uint32_t busy;               /*0x08 */
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	/*
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	 * Set by the Net Device.
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	 * The device will set it once data has been received.
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	 * The value is the number of bytes that should be read from
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	 * rxDataBuffer.  The value will decrease till 0 until all the data
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	 * from rxDataBuffer has been read.
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	 */
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	uint32_t rxDataCount;        /*0x0c */
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#define MIPSNET_MAX_RXTX_DATACOUNT (1 << 16)
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	/*
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	 * Settable from the MIPS core, cleared by the Net Device.
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	 * The core should set the number of bytes it wants to send,
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	 * then it should write those bytes of data to txDataBuffer.
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	 * The device will clear txDataCount has been processed (not
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	 * necessarily sent).
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	 */
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	uint32_t txDataCount;        /*0x10 */
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	/*
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	 * Interrupt control
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	 *
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	 * Used to clear the interrupted generated by this dev.
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	 * Write a 1 to clear the interrupt. (except bit31).
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	 *
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	 * Bit0 is set if it was a tx-done interrupt.
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	 * Bit1 is set when new rx-data is available.
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	 *    Until this bit is cleared there will be no other RXs.
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	 *
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	 * Bit31 is used for testing, it clears after a read.
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	 *    Writing 1 to this bit will cause an interrupt to be generated.
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	 *    To clear the test interrupt, write 0 to this register.
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	 */
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	uint32_t interruptControl;   /*0x14 */
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#define MIPSNET_INTCTL_TXDONE     (1u << 0)
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#define MIPSNET_INTCTL_RXDONE     (1u << 1)
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#define MIPSNET_INTCTL_TESTBIT    (1u << 31)
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	/*
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	 * Readonly core-specific interrupt info for the device to signal
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	 * the core. The meaning of the contents of this field might change.
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	 */
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	/* XXX: the whole memIntf interrupt scheme is messy: the device
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	 * should have no control what so ever of what VPE/register set is
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	 * being used.
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	 * The MemIntf should only expose interrupt lines, and something in
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	 * the config should be responsible for the line<->core/vpe bindings.
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	 */
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	uint32_t interruptInfo;      /*0x18 */
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	/*
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	 * This is where the received data is read out.
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	 * There is more data to read until rxDataReady is 0.
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	 * Only 1 byte at this regs offset is used.
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	 */
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	uint32_t rxDataBuffer;       /*0x1c */
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	/*
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	 * This is where the data to transmit is written.
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	 * Data should be written for the amount specified in the
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	 * txDataCount register.
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	 * Only 1 byte at this regs offset is used.
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	 */
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	uint32_t txDataBuffer;       /*0x20 */
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};
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static int mipsnet_xmit(struct net_device *dev, struct sk_buff *skb) {
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	struct mipsnet_regs *regs;
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	int i;
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	uint8_t *pdata;
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	show_packet(skb->mac.raw, skb->len, "xmit");
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	regs = (struct mipsnet_regs *)dev->base_addr;
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	pdata = skb->mac.raw;
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	out32(skb->len, &regs->txDataCount);
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	for(i = 0; i < skb->len; i++) {
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		out32((uint32_t)*pdata, &regs->txDataBuffer);
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		pdata++;
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	}
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	skb_free(skb);
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	return 0;
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}
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static int mipsnet_open(struct net_device *dev) {
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	struct mipsnet_regs *regs;
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	regs = (struct mipsnet_regs *)dev->base_addr;
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	out32(MIPSNET_INTCTL_TESTBIT, &regs->interruptControl);
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	return 0;
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}
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static int mipsnet_set_macaddr(struct net_device *dev, const void *addr) {
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	return 0;
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}
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static const struct net_driver mipsnet_drv_ops = {
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	.xmit = mipsnet_xmit,
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	.start = mipsnet_open,
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	.set_macaddr = mipsnet_set_macaddr
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};
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static int mipsnet_rx(struct net_device *dev, size_t len) {
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	struct sk_buff *skb;
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	uint8_t *pdata;
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	struct mipsnet_regs *regs;
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	if (!len)
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			return len;
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	regs = (struct mipsnet_regs *)dev->base_addr;
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	skb = skb_alloc(len);
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	if (!skb) {
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			dev->stats.rx_dropped++;
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			return -ENOMEM;
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	}
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	pdata = (uint8_t*) skb->mac.raw;
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	for (; len > 0; len--, pdata++) {
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		*pdata = in32(&regs->rxDataBuffer);
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	}
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	show_packet(skb->mac.raw, skb->len, "rx");
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	skb->dev = dev;
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	netif_rx(skb);
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	dev->stats.rx_packets++;
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	dev->stats.rx_bytes += len;
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	return len;
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}
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static irq_return_t mipsnet_interrupt_handler(unsigned int irq, void *dev_id) {
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	struct net_device *dev = dev_id;
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	uint32_t int_flags;
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	irq_return_t ret = IRQ_NONE;
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	struct mipsnet_regs *regs;
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	if (irq != dev->irq)
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		goto out_badirq;
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	regs = (struct mipsnet_regs *)dev->base_addr;
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	/* TESTBIT is cleared on read. */
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	int_flags = in32(&regs->interruptControl);
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	if (int_flags & MIPSNET_INTCTL_TESTBIT) {
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			/* TESTBIT takes effect after a write with 0. */
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			out32(0, &regs->interruptControl);
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			ret = IRQ_HANDLED;
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	} else if (int_flags & MIPSNET_INTCTL_TXDONE) {
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			/* Only one packet at a time, we are done. */
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			dev->stats.tx_packets++;
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			out32(MIPSNET_INTCTL_TXDONE, &regs->interruptControl);
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			ret = IRQ_HANDLED;
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	} else if (int_flags & MIPSNET_INTCTL_RXDONE) {
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			mipsnet_rx(dev, in32(&regs->rxDataCount));
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			out32(MIPSNET_INTCTL_RXDONE, &regs->interruptControl);
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			ret = IRQ_HANDLED;
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	}
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	return ret;
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out_badirq:
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	 log_info("%s: irq %d for unknown device\n", dev->name, irq);
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	 return ret;
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}
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static int mipsnet_init(void) {
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	struct net_device *netdev;
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	int err;
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	netdev = etherdev_alloc(0);
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	if (!netdev) {
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		return -ENOMEM;
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	}
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	/*
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	 * TODO: probe for these or load them from PARAM
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	 */
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	netdev->base_addr = BASE_ADDR;
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	netdev->irq = IRQ_NUM;
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	netdev->drv_ops = &mipsnet_drv_ops;
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	err = irq_attach(IRQ_NUM, mipsnet_interrupt_handler, 0, netdev, "mipsnet");
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	if (err) {
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		return err;
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	}
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	return inetdev_register_dev(netdev);
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}
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