embox

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/**
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 * @file cadence_gem.c
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 *
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 * @date 06.03.20
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 * @author: Nastya Nizharadze
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 *
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 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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 */
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#include <errno.h>
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#include <stdint.h>
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#include <util/log.h>
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#include <kernel/irq.h>
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#include <net/skbuff.h>
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#include <net/l0/net_entry.h>
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#include <net/l2/ethernet.h>
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#include <net/inetdevice.h>
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#include <net/util/show_packet.h>
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#include <asm/regs.h>
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#include <string.h>
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#include <embox/unit.h>
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#include <net/skbuff.h>
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#include <net/netdevice.h>
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#include <asm/io.h>
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#include <hal/reg.h>
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#include <stdio.h>
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#include <kernel/printk.h>
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#define BASE_ADDR			OPTION_GET(NUMBER,base_addr)
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#define SIFIVE_U_GEM_IRQ	OPTION_GET(NUMBER,irq_num)
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#define GEM_NWCTRL        0x00000000 /* Network Control */
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#define GEM_NWCFG         0x00000004 /* Network Config */
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#define GEM_NWSTATUS      0x00000008 /* Network Status */
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#define GEM_USERIO        0x0000000C /* User IO */
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#define GEM_DMACFG        0x00000010 /* DMA Control */
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#define GEM_TXSTATUS      0x00000014 /* TX Status */
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#define GEM_RXQBASE       0x00000018 /* RX Q Base address */
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#define GEM_TXQBASE       0x0000001C /* TX Q Base address */
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#define GEM_RXSTATUS      0x00000020 /* RX Status */
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#define GEM_ISR           0x00000024 /* Interrupt Status */
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#define GEM_IER           0x00000028 /* Interrupt Enable */
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#define GEM_IDR           0x0000002C /* Interrupt Disable */
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#define GEM_IMR           0x00000030 /* Interrupt Mask */
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#define GEM_PHYMNTNC      0x00000034 /* Phy Maintenance */
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#define GEM_SPADDR1LO     0x00000088 /* Specific addr 1 low reg */
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#define GEM_SPADDR1HI     0x0000008C /* Specific addr 1 high reg */
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#define GEM_TXSTATUS_TXCMPL    0x00000020 /* Transmit Complete */
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#define GEM_TXSTATUS_USED      0x00000001
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#define GEM_NWCTRL_TXENA       0x00000008 /* Transmit Enable */
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#define GEM_NWCTRL_TXSTART     0x00000200 /* Transmit Enable */
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#define GEM_NWCTRL_RXENA       0x00000004 /* Receive Enable */
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#define GEM_NWCFG_STRIP_FCS    0x00020000 /* Strip FCS field */
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#define DESC_1_USED		0x80000000
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#define DESC_1_LENGTH	0x00001FFF
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#define DESC_1_TX_WRAP	0x40000000
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#define DESC_1_TX_LAST	0x00008000
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#define DESC_0_RX_WRAP		0x00000002
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#define DESC_0_RX_OWNERSHIP	0x00000001
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#define GEM_INT_TXCMPL	0x00000080 /* Transmit Complete */
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#define GEM_INT_TXUSED	0x00000008
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#define GEM_INT_RXUSED	0x00000004
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#define GEM_INT_RXCMPL	0x00000002
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#define GEM_TXDESC_LAST_BUF			(1 << 15)  /* last in frame */
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#define GEM_TXDESC_USED			(1U << 31) /* done txmitting */
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#define GEM_TXDESC_WRAP			(1 << 30)  /* end descr ring */
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#define GEM_RXDESC_EOF				(1 << 15) /* end of frame */
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#define GEM_RXDESC_SOF				(1 << 14) /* start of frame */
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#define GEM_INTR_STAT			0x024	/* Interrupt Status */
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#define GEM_RX_STAT			0x020	/* Receive Status */
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#define GEM_DMA_CFG_RX_BUF_SIZE(sz)		((((sz) + 63) / 64)  <<  16)
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#define MAX_BUFF_SIZE 1600
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int fst_xmit = 0;
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struct dma_desc_rx {
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	uint32_t addr;
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	uint32_t flags;
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} dma_desc_rx __attribute__((aligned(4)));
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struct dma_desc_tx {
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	uint32_t addr;
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	uint32_t flags;
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} dma_desc_tx __attribute__((aligned(4)));
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unsigned char rx_buff[MAX_BUFF_SIZE] __attribute__((aligned(4)));
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unsigned char tx_buff[MAX_BUFF_SIZE] __attribute__((aligned(4)));
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static int cadence_gem_xmit(struct net_device *dev, struct sk_buff *skb) {
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  uint32_t net_control;
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  uint32_t tx_stat;
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  tx_stat = REG32_LOAD((uint32_t)BASE_ADDR + (uint32_t)GEM_TXSTATUS);
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  tx_stat |= GEM_TXSTATUS_TXCMPL;
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  REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_TXSTATUS), tx_stat);
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  memset(tx_buff, 0, sizeof(char) * MAX_BUFF_SIZE);
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  memcpy(tx_buff, skb->mac.raw, skb->len);
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  dma_desc_tx.addr = (uint32_t) tx_buff;
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  dma_desc_tx.flags &= 0xffffc000;
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  dma_desc_tx.flags |= (skb->len);
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  dma_desc_tx.flags |= GEM_TXDESC_LAST_BUF;
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  dma_desc_tx.flags &= ~GEM_TXDESC_USED;
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  //show_packet(skb->mac.raw, skb->len, "xmit");
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  net_control = REG32_LOAD((uint32_t)BASE_ADDR + (uint32_t)GEM_NWCTRL);
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  net_control |= GEM_NWCTRL_TXSTART;
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  REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_NWCTRL), net_control);
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  skb_free(skb);
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  return 0;
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}
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static void program_dma_cfg(void) {
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	uint32_t val = 0;
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	val |= GEM_DMA_CFG_RX_BUF_SIZE(MAX_BUFF_SIZE);
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_DMACFG), val);
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}
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static int cadence_gem_start(struct net_device *dev) {
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	uint32_t net_control;
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	uint32_t net_config;
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	uint32_t net_ier;
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	unsigned char mac_addr[6] = {0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x02};
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	program_dma_cfg();
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_SPADDR1LO), (uint32_t)*(uint32_t *)mac_addr);
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_SPADDR1HI), (uint16_t)*(uint16_t *)(mac_addr + 4));
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	dma_desc_tx.flags = DESC_1_USED & DESC_1_TX_WRAP & DESC_1_TX_LAST;
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	dma_desc_tx.addr = 0;
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	dma_desc_tx.flags = 0;
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	dma_desc_tx.flags = (0u << 31) | GEM_TXDESC_WRAP;
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	dma_desc_rx.addr = (uint32_t)rx_buff | DESC_0_RX_WRAP;
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	dma_desc_rx.flags = 0;
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	net_config = REG32_LOAD((uint32_t)BASE_ADDR + (uint32_t)GEM_NWCFG);
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	net_config |= GEM_NWCFG_STRIP_FCS;
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_NWCFG), net_config);
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_RXQBASE), (uint32_t)&dma_desc_rx);
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_TXQBASE), (uint32_t)&dma_desc_tx);
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	net_ier =REG32_LOAD((uint32_t)BASE_ADDR + (uint32_t)GEM_IER);
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	net_ier |= GEM_INT_TXCMPL | GEM_INT_TXUSED | GEM_INT_RXUSED | GEM_INT_RXCMPL;
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_IER), net_ier);
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	net_control = REG32_LOAD((uint32_t)BASE_ADDR + (uint32_t)GEM_NWCTRL);
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	net_control |= GEM_NWCTRL_TXENA;
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	net_control |= GEM_NWCTRL_RXENA;
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_NWCTRL), net_control);
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	return 0;
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}
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static int cadence_gem_set_macaddr(struct net_device *dev, const void *addr) {
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	return 0;
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}
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static const struct net_driver cadence_gem_drv_ops = {
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	.xmit = cadence_gem_xmit,
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	.start = cadence_gem_start,
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	.set_macaddr = cadence_gem_set_macaddr
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};
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static int cadence_gem_rx(struct net_device *dev) {
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	uint32_t net_control;
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	struct sk_buff *skb;
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	if (!(dma_desc_rx.addr & DESC_0_RX_OWNERSHIP)){
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		dma_desc_tx.flags &= ~DESC_1_LENGTH;
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		dma_desc_rx.addr &= ~DESC_0_RX_OWNERSHIP;
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		return 0;
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	}
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	uint32_t ctl = dma_desc_rx.flags;
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	if ((ctl & (GEM_RXDESC_SOF | GEM_RXDESC_EOF)) !=
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		(GEM_RXDESC_SOF | GEM_RXDESC_EOF)) {
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		return 0;
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	}
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	skb = skb_alloc(dma_desc_rx.flags & DESC_1_LENGTH);
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	if (!skb) {
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			dev->stats.rx_dropped++;
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			return -ENOMEM;
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	}
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	skb->len = (dma_desc_rx.flags & DESC_1_LENGTH);
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	memcpy(skb->mac.raw, rx_buff, skb->len);
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	dma_desc_rx.addr = (uint32_t)rx_buff | DESC_0_RX_WRAP;
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	dma_desc_tx.flags &= ~DESC_1_LENGTH;
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	net_control = REG32_LOAD((uint32_t)BASE_ADDR + (uint32_t)GEM_NWCTRL);
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	net_control |= GEM_NWCTRL_RXENA;
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_NWCTRL), net_control);
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	//show_packet(skb->mac.raw, skb->len, "rx");
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	skb->dev = dev;
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	netif_rx(skb);
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	dev->stats.rx_packets++;
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	dev->stats.rx_bytes += skb->len;
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	return 0;
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}
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static irq_return_t cadence_gem_interrupt_handler(unsigned int irq,
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												  void *dev_id) {
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	struct net_device *dev = dev_id;
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	uint32_t istatus;
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	/* Read and clear registers */
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	istatus = REG32_LOAD((uint32_t)BASE_ADDR + (uint32_t)GEM_INTR_STAT);
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_INTR_STAT), istatus);
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_RX_STAT), istatus);
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	REG32_STORE(((uint32_t)BASE_ADDR + (uint32_t)GEM_RX_STAT), 0xf);
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	cadence_gem_rx(dev);
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	return 0;
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}
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static int cadence_gem_init(void) {
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	struct net_device *netdev;
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	int err;
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	netdev = etherdev_alloc(0);
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	if (!netdev) {
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		return -ENOMEM;
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	}
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	netdev->base_addr = BASE_ADDR;
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	netdev->irq = SIFIVE_U_GEM_IRQ;
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	netdev->drv_ops = &cadence_gem_drv_ops;
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	err = irq_attach(SIFIVE_U_GEM_IRQ, cadence_gem_interrupt_handler, 
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									 0, netdev, "cadence_gem");
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	if (err) {
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		return err;
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	}
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	return inetdev_register_dev(netdev);
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}
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EMBOX_UNIT_INIT(cadence_gem_init);
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