embox

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/**
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 * @file
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 *
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 * @brief PLIC interrupt driver for SiFive U54-MC Core
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 *
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 * @date 08.06.2024
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 * @author Suraj Sonawane
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 */
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#include <assert.h>
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#include <stdint.h>
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#include <asm/interrupts.h>
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#include <asm/regs.h>
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#include <drivers/irqctrl.h>
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#include <embox/unit.h>
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#include <hal/reg.h>
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#include <util/log.h>
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#define SIFIVE_PLIC_BASE_ADDR            0x0C000000UL /* Base address for SiFive PLIC */
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#define SIFIVE_PLIC_PRIORITY_OFFSET      0x00000000UL
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#define SIFIVE_PLIC_PENDING_OFFSET       0x00001000UL
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#define SIFIVE_PLIC_ENABLE_OFFSET        0x00002000UL
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#define SIFIVE_PLIC_THRESHOLD_OFFSET     0x00200000UL
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#define SIFIVE_PLIC_CLAIM_OFFSET         0x00200004UL
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#define SIFIVE_PLIC_PRIORITY_REG(interrupt_id) (SIFIVE_PLIC_BASE_ADDR + SIFIVE_PLIC_PRIORITY_OFFSET + (interrupt_id) * 4)
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#define SIFIVE_PLIC_PENDING_REG(word_index)    (SIFIVE_PLIC_BASE_ADDR + SIFIVE_PLIC_PENDING_OFFSET + (word_index) * 4)
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#define SIFIVE_PLIC_ENABLE_REG(hart_id, word_index) (SIFIVE_PLIC_BASE_ADDR + SIFIVE_PLIC_ENABLE_OFFSET + (hart_id) * 0x80 + (word_index) * 4)
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#define SIFIVE_PLIC_THRESHOLD_REG(hart_id)     (SIFIVE_PLIC_BASE_ADDR + SIFIVE_PLIC_THRESHOLD_OFFSET + (hart_id) * 0x1000)
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#define SIFIVE_PLIC_CLAIM_REG(hart_id)         (SIFIVE_PLIC_BASE_ADDR + SIFIVE_PLIC_CLAIM_OFFSET + (hart_id) * 0x1000)
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#define SIFIVE_PLIC_MAX_INTERRUPTS 511
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#define SIFIVE_PLIC_MAX_PRIORITY 7
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static int sifive_plic_init(void) {
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    for (uint32_t hart_id = 0; hart_id < 4; hart_id++) {
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        REG32_STORE(SIFIVE_PLIC_THRESHOLD_REG(hart_id), 0);
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    }
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    enable_external_interrupts();
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    return 0;
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}
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void irqctrl_set_prio(unsigned int interrupt_nr, unsigned int prio) {
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    if (interrupt_nr > 0 && interrupt_nr <= SIFIVE_PLIC_MAX_INTERRUPTS) {
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        if (prio <= SIFIVE_PLIC_MAX_PRIORITY) {
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            REG32_STORE(SIFIVE_PLIC_PRIORITY_REG(interrupt_nr), prio);
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        } else {
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            log_error("Priority value %u exceeds the maximum allowable priority %u",
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                      prio, SIFIVE_PLIC_MAX_PRIORITY);
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        }
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    } else {
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        log_error("Interrupt number %u is out of valid range (1 to %u)",
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                  interrupt_nr, SIFIVE_PLIC_MAX_INTERRUPTS);
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    }
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}
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void irqctrl_enable_in_cpu(uint32_t hart_id, unsigned int interrupt_nr) {
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    if (interrupt_nr > 0 && interrupt_nr <= SIFIVE_PLIC_MAX_INTERRUPTS) {
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        uint32_t reg;
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        uint32_t word_index = interrupt_nr / 32;
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        uint32_t bit_index = interrupt_nr % 32;
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        REG32_STORE(SIFIVE_PLIC_PRIORITY_REG(interrupt_nr), 1);
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        reg = REG32_LOAD(SIFIVE_PLIC_ENABLE_REG(hart_id, word_index));
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        reg |= (1U << bit_index);
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        REG32_STORE(SIFIVE_PLIC_ENABLE_REG(hart_id, word_index), reg);
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    } else {
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        log_error("Interrupt number %u is out of valid range (1 to %u)",
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                  interrupt_nr, SIFIVE_PLIC_MAX_INTERRUPTS);
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    }
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}
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void irqctrl_disable_in_cpu(uint32_t hart_id, unsigned int interrupt_nr) {
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    if (interrupt_nr > 0 && interrupt_nr <= SIFIVE_PLIC_MAX_INTERRUPTS) {
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        uint32_t reg;
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        uint32_t word_index = interrupt_nr / 32;
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        uint32_t bit_index = interrupt_nr % 32;
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        reg = REG32_LOAD(SIFIVE_PLIC_ENABLE_REG(hart_id, word_index));
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        reg &= ~(1U << bit_index);
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        REG32_STORE(SIFIVE_PLIC_ENABLE_REG(hart_id, word_index), reg);
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    } else {
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        log_error("Interrupt number %u is out of valid range (1 to %u)",
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                  interrupt_nr, SIFIVE_PLIC_MAX_INTERRUPTS);
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    }
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}
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void irqctrl_eoi_in_cpu(uint32_t hart_id, unsigned int irq) {
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    REG32_STORE(SIFIVE_PLIC_CLAIM_REG(hart_id), irq);
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}
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unsigned int irqctrl_get_intid_from_cpu(uint32_t hart_id) {
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    return REG32_LOAD(SIFIVE_PLIC_CLAIM_REG(hart_id));
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}
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IRQCTRL_DEF(sifive_plic, sifive_plic_init);