embox

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/**
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 * @file
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 * @brief MIPS build-in interrupt controller
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 *
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 * @date 04.07.2012
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 * @author Anton Bondarev
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 */
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#include <assert.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <asm/mipsregs.h>
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#include <drivers/irqctrl.h>
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#include <kernel/irq.h>
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void irqctrl_enable(unsigned int irq) {
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	uint32_t c0;
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	assert(irq_nr_valid(irq));
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	c0 = mips_read_c0_status();
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	c0 |= 1U << (irq + ST0_IRQ_MASK_OFFSET);
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	mips_write_c0_status(c0);
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}
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void irqctrl_disable(unsigned int irq) {
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	uint32_t c0;
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	assert(irq_nr_valid(irq));
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	c0 = mips_read_c0_status();
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	c0 &= ~(1U << (irq + ST0_IRQ_MASK_OFFSET));
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	mips_write_c0_status(c0);
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}
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void irqctrl_force(unsigned int irq) {
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}
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int irqctrl_pending(unsigned int irq) {
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	return 0;
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}
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void irqctrl_eoi(unsigned int irq) {
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}
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unsigned int irqctrl_get_intid(void) {
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	unsigned int irq;
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	uint32_t pending;
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	pending = (mips_read_c0_cause() & CAUSE_IM) >> ST0_IRQ_MASK_OFFSET;
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	for (irq = 0; irq < IRQCTRL_IRQS_TOTAL; irq++) {
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		if (pending & (1U << irq)) {
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			return irq;
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		}
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	}
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	return -1;
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}
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IRQCTRL_DEF(mips_intc, NULL);
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