embox

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/**
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 * @file
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 *
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 * @date Mar 23, 2020
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 * @author Anton Bondarev
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 */
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#include <assert.h>
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#include <stdint.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <drivers/mips/global_control_block.h>
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#include <framework/mod/options.h>
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#include <hal/reg.h>
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#include <kernel/irq.h>
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#include <util/log.h>
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#include "mips_gic_regs.h"
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#define MIPS_GIC_BASE OPTION_GET(NUMBER, base_addr)
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static int mips_gic_init(void) {
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	uint32_t c0;
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	int i;
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#if (MIPS_GIC_BASE < (0xA0000000))
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	mips32_gcb_set_register(GCR_GIC_BASE, MIPS_GIC_BASE | GIC_EN);
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#else
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	mips32_gcb_set_register(GCR_GIC_BASE,
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	    (MIPS_GIC_BASE - (0xA0000000)) | GIC_EN);
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#endif /* (MIPS_GIC_BASE < (0xA0000000)) */
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	__sync();
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	for (i = 0; i < __IRQCTRL_IRQS_TOTAL; i++) {
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		if (0 == (i & 0x1F)) {
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			REG32_STORE((MIPS_GIC_BASE + GIC_SH_RMASK(i)), 0xFFFFFFFF);
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			REG32_STORE(MIPS_GIC_BASE + GIC_SH_POL(i), 0xFFFFFFFF);
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		}
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		/* only 1 cpu core */
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		REG32_STORE(MIPS_GIC_BASE + GIC_SH_MAP_CORE31_0(i), 0x1);
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		REG32_STORE(MIPS_GIC_BASE + GIC_SH_MAP_PIN(i),
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		    MIPS_GIC_INTERRUPT_PIN | 1u << 31);
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	}
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	c0 = mips_read_c0_status();
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	c0 |= 1 << (MIPS_GIC_INTERRUPT_PIN + ST0_IRQ_MASK_OFFSET + ST0_SOFTIRQ_NUM);
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	mips_write_c0_status(c0);
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	log_info("mips_gic config %x\n", REG_LOAD(MIPS_GIC_BASE + GIC_SH_CONFIG));
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	log_info("mips_gic revision %x\n", REG_LOAD(MIPS_GIC_BASE + GIC_SH_REVID));
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	return 0;
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}
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void irqctrl_enable(unsigned int irq) {
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	uint32_t mask;
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	uint32_t reg;
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	uint32_t c0;
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	assert(irq_nr_valid(irq));
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	if (irq < 8) {
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		c0 = mips_read_c0_status();
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		c0 |= 1 << (irq + ST0_IRQ_MASK_OFFSET);
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		mips_write_c0_status(c0);
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	}
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	else {
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		reg = irq >> 5;
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		mask = (1 << (irq & 0x1F));
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		REG32_STORE(MIPS_GIC_BASE + GIC_SH_SMASK(reg << 5), mask);
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	}
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}
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void irqctrl_disable(unsigned int irq) {
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	uint32_t mask;
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	uint32_t reg;
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	uint32_t c0;
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	assert(irq_nr_valid(irq));
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	if (irq < 8) {
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		c0 = mips_read_c0_status();
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		c0 &= ~(1 << (irq + ST0_IRQ_MASK_OFFSET));
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		mips_write_c0_status(c0);
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	}
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	else {
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		reg = irq >> 5;
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		mask = (1 << (irq & 0x1F));
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		REG32_STORE(MIPS_GIC_BASE + GIC_SH_RMASK(reg << 5), mask);
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	}
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}
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void irqctrl_force(unsigned int irq) {
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}
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int irqctrl_pending(unsigned int irq) {
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	return 0;
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}
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void irqctrl_eoi(unsigned int irq) {
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	uint32_t mask;
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	uint32_t reg;
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	assert(irq_nr_valid(irq));
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	/* XXX */
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	if (irq >= 8) {
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		reg = irq >> 5;
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		mask = (1 << (irq & 0x1F));
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		REG32_STORE(MIPS_GIC_BASE + GIC_SH_SMASK(reg << 5), mask);
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	}
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}
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unsigned int irqctrl_get_intid(void) {
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	uint32_t pending;
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	int i, j;
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	pending = (mips_read_c0_cause() & CAUSE_IM) >> ST0_IRQ_MASK_OFFSET;
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	if (!(pending & (0x1 << (ST0_SOFTIRQ_NUM + MIPS_GIC_INTERRUPT_PIN)))) {
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		for (i = 0; i < 8; i++) {
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			if (pending & (1U << i)) {
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				return i;
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			}
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		}
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	}
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	for (i = 0; i < __IRQCTRL_IRQS_TOTAL; i += 32) {
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		pending = REG32_LOAD(MIPS_GIC_BASE + GIC_SH_PEND(i));
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		pending &= REG32_LOAD(MIPS_GIC_BASE + GIC_SH_MASK(i));
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		if (!pending) {
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			continue;
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		}
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		for (j = 0; j < 32; j++) {
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			if (pending & (1U << j)) {
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				return i + j;
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			}
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		}
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	}
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	return -1;
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}
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IRQCTRL_DEF(mips_gic, mips_gic_init);
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