embox

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/**
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 * @file
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 * @brief Low level functions for interrupt controller.
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 *
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 * @date 23.11.09
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 * @author Anton Bondarev
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 */
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#include <stdint.h>
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#include <drivers/common/memory.h>
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#include <asm/bitops.h>
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#include <hal/reg.h>
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#include <drivers/irqctrl.h>
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#include <embox/unit.h>
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#include <module/embox/driver/interrupt/mb_intc.h>
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#define CONFIG_XILINX_INTC_BASEADDR OPTION_GET(NUMBER,mbintc_base)
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/**
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 * Microblaze interrupt controller registers definitions.
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 */
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struct irqc_regs {
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	/* 0x00 */uint32_t isr; /**< interrupt status register */
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	/* 0x04 */uint32_t ipr; /**< interrupt pending register */
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	/* 0x08 */uint32_t ier; /**< interrupt enable register */
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	/* 0x0C */uint32_t iar; /**< interrupt acknowledge register */
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	/* 0x10 */uint32_t sie; /**< set interrupt enable bits */
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	/* 0x14 */uint32_t cie; /**< clear interrupt enable bits */
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	/* 0x18 */uint32_t ivr; /**< interrupt vector register */
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	/* 0x1C */uint32_t mer; /**< master enable register */
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};
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#define MER_HIE_BIT     30
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#define MER_ME_BIT      31
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#define MER_HIE         REVERSE_MASK(MER_HIE_BIT)
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#define MER_ME          REVERSE_MASK(MER_ME_BIT)
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static volatile struct irqc_regs *irqc =
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		(struct irqc_regs *) CONFIG_XILINX_INTC_BASEADDR;
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static int mb_intc_init(void) {
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	irqc->mer = 0;
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	irqc->ier = 0;
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	irqc->iar = ~(0x0);
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	/* after set HIE bit we will not can clear it again.
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	 * It's a problem because we will couldn't testing interrupts by soft
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	 * (we will could use function irqc_force).
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	 */
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	irqc->mer = MER_HIE | MER_ME;
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	return 0;
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}
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void irqctrl_enable(unsigned int irq) {
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	REG_STORE(&irqc->sie, 1UL << irq);
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}
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void irqctrl_disable(unsigned int irq) {
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	REG_STORE(&irqc->cie, 1UL << irq);
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}
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//TODO this not set in microblaze
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void irqctrl_force(unsigned int irq_num) {
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}
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void irqctrl_clear(unsigned int irq) {
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	REG_STORE(&irqc->iar, 1UL << irq);
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}
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int irqctrl_pending(unsigned int irq) {
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	return REG_LOAD(&irqc->isr) & (1 << irq);
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}
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/* microblaze specific */
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unsigned int irqctrl_get_irq_num(void) {
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	return REG_LOAD(&irqc->ivr);
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}
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PERIPH_MEMORY_DEFINE(mb_intc, CONFIG_XILINX_INTC_BASEADDR, sizeof(struct irqc_regs));
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IRQCTRL_DEF(mb_intc, mb_intc_init);
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