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/**
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 * @file
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 * @brief
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 *
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 * @author Aleksey Zhmulin
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 * @date 20.10.23
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 */
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#include <assert.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <drivers/common/memory.h>
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#include <drivers/irqctrl.h>
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#include <framework/mod/options.h>
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#include <hal/reg.h>
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#include <kernel/critical.h>
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#include <kernel/irq.h>
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#include <kernel/printk.h>
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#include <util/field.h>
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#include <util/log.h>
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#include "gicv1.h"
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#define GIC_SPURIOUS_IRQ 0x3FF
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static int gic_irqctrl_init(void) {
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	uint32_t reg;
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	/* Enable interrupts of all priorities */
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	reg = REG32_LOAD(GICC_PMR);
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	reg = FIELD_SET(reg, GICD_PMR_PRIOR, 0xff);
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	REG32_STORE(GICC_PMR, reg);
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	/* Configure control registers */
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	REG32_ORIN(GICD_CTLR, GICD_CTLR_EN);
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	REG32_ORIN(GICC_CTLR, GICC_CTLR_EN);
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	/* Print info */
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	reg = REG32_LOAD(GICD_TYPER);
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	log_info("Number of SPI: %zi",
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	    (size_t)(FIELD_GET(reg, GICD_TYPER_ITLINES) * 32));
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	log_info("Number of supported CPU interfaces: %zi",
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	    (size_t)FIELD_GET(reg, GICD_TYPER_CPU));
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	if (reg & GICD_TYPER_SECEXT) {
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		log_info("Secutity Extension implemented");
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		log_info("Number of LSPI: %zi",
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		    (size_t)FIELD_GET(reg, GICD_TYPER_LSPI));
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	}
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	else {
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		log_info("Secutity Extension not implemented");
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		log_info("LSPI not implemented");
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	}
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	return 0;
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}
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void irqctrl_enable(unsigned int irq) {
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	unsigned int reg_nr;
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	uint32_t value;
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	assert(irq_nr_valid(irq));
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	reg_nr = irq >> 5;
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	value = 1U << (irq & 0x1f);
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	/* Writing zeroes to this register has no
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	 * effect, so we just write single "1" */
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	REG32_STORE(GICD_ISENABLER(reg_nr), value);
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	/* N-N irq model: all CPUs receive this IRQ */
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	REG32_STORE(GICD_ICFGR(reg_nr), value);
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	/* All CPUs do listen to this IRQ */
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	reg_nr = irq >> 2;
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	value = 0xff << ((irq & 0x3) << 3);
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	REG32_ORIN(GICD_ITARGETSR(reg_nr), value);
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}
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void irqctrl_disable(unsigned int irq) {
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	unsigned int reg_nr;
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	uint32_t value;
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	assert(irq_nr_valid(irq));
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	reg_nr = irq >> 5;
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	value = 1U << (irq & 0x1f);
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	/* Writing zeroes to this register has no
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	 * effect, so we just write single "1" */
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	REG32_STORE(GICD_ICENABLER(reg_nr), value);
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}
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void irqctrl_force(unsigned int irq) {
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}
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int irqctrl_pending(unsigned int irq) {
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	return 0;
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}
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/* Sends an EOI (end of interrupt) signal to the PICs. */
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void irqctrl_eoi(unsigned int irq) {
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	assert(irq_nr_valid(irq));
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	REG32_STORE(GICC_EOIR, irq);
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}
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unsigned int irqctrl_get_intid(void) {
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	unsigned int irq;
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	irq = REG32_LOAD(GICC_IAR);
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	if (irq == GIC_SPURIOUS_IRQ) {
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		irq = -1;
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	}
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	return irq;
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}
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IRQCTRL_DEF(gicv1, gic_irqctrl_init);
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PERIPH_MEMORY_DEFINE(gicd, GICD_BASE, 0x1000);
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PERIPH_MEMORY_DEFINE(gicc, GICC_BASE, 0x2020);
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