embox

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/**
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 * @file
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 * @brief
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 *
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 * @date 18.12.2012
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 * @author Anton Bulychev
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 */
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#include <embox/unit.h>
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#include <drivers/common/memory.h>
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#include "lapic.h"
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#ifdef LAPIC_REGS_X86_H_
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#include <asm/msr.h>
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#include <asm/ap.h>
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#endif
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#include <kernel/panic.h>
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#include <hal/cpu.h>
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#define lapic_read_icr1()    lapic_read(LAPIC_ICR1)
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#define lapic_read_icr2()    lapic_read(LAPIC_ICR2)
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#define lapic_write_icr1(val)   lapic_write(LAPIC_ICR1, val)
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#define lapic_write_icr2(val)   lapic_write(LAPIC_ICR2, val)
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#define	TMR_PERIODIC     0x20000
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#define	TMR_BASEDIV      (1<<20)
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static void udelay(int delay) {
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	volatile int i;
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	for (i = delay * 10; i != 0; i-- );
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}
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void lapic_send_init_ipi(uint32_t apic_id) {
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	uint32_t val;
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	val = (apic_id & 0xFF) << 24; /* Destination Field */
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	lapic_write_icr2(val);
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	/* since target cpu is not init yet, this ipi MUST in physical mode */
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	val = LAPIC_ICR_DM_INIT; /* Delivery Mode: INIT */
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	val |= LAPIC_ICR_INT_ASSERT; /* Level: Assert */
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	val |= LAPIC_ICR_DEST_FIELD; /* Destination Shorthand: field specified*/
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	val |= LAPIC_ICR_INIT_LEVELTRIG;/*triger level: set high level*/	
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	lapic_write_icr1(val);
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	udelay(10000);
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	/* sleep until Delivery Status is Pending */
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	while (lapic_read_icr1() & LAPIC_ICR_DELIVERY_PENDING);
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}
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void lapic_send_startup_ipi(uint32_t apic_id, uint32_t trampoline) {
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	uint32_t val;
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	val = (apic_id & 0xFF) << 24; /* Destination Field */
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	lapic_write_icr2(val);
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	/* since target cpu is not init yet, this ipi MUST in physical mode */
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	val = (trampoline >> 12) & 0xFF; /* Vector Field */
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	val |= LAPIC_ICR_DM_FIXED; /* Delivery Mode: FIXED */
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	val |= LAPIC_ICR_DM_STARTUP; /* Delivery Mode: Start Up */
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	val |= LAPIC_ICR_DEST_FIELD; /* Destination Shorthand: field specified*/
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	lapic_write_icr1(val);
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	udelay(1000);
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	val = (trampoline >> 12) & 0xFF; /* Vector Field */
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	val |= LAPIC_ICR_DM_FIXED; /* Delivery Mode: FIXED */
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	val |= LAPIC_ICR_DM_STARTUP; /* Delivery Mode: Start Up */
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	val |= LAPIC_ICR_DEST_FIELD; /* Destination Shorthand: field specified*/
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	lapic_write_icr1(val);
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	udelay(1000);
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	/* sleep until Delivery Status is Pending */
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	while (lapic_read_icr1() & LAPIC_ICR_DELIVERY_PENDING);
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}
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void lapic_send_ipi(unsigned int vector, unsigned int cpu, int type) {
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	uint32_t icr1, icr2;
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	while (lapic_read_icr1() & LAPIC_ICR_DELIVERY_PENDING) {
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		panic("Not implemented\n");
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	}
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	/* Clear all ICR state */
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	icr1 = icr2 = 0;
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	switch (type) {
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		case LAPIC_ICR_DEST_FIELD:
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			lapic_write_icr2(icr2 |	(cpu << 24));
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			lapic_write_icr1(icr1 |	type | LAPIC_ICR_LOGICAL_DEST | vector);
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			break;
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		case LAPIC_ICR_DEST_SELF:
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			/* Do not care about the delivery mode */
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			lapic_write_icr2(icr2);
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			lapic_write_icr1(icr1 |	type | vector);
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			break;
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		case LAPIC_ICR_DEST_ALL:
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			/* Do not care about the delivery mode */
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			lapic_write_icr2(icr2);
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			lapic_write_icr1(icr1 |	type | vector);
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			break;
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		case LAPIC_ICR_DEST_ALL_BUT_SELF:
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			/* Do not care about the delivery mode */
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			lapic_write_icr2(icr2);
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			lapic_write_icr1(icr1 |	type | vector);
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			break;
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		default:
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			panic("Unknown send ipi type request\n");
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			break;
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	}
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}
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static inline void lapic_enable_in_msr(void) {
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#ifdef LAPIC_REGS_X86_H_ /* Needed only on x86 */
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	uint32_t msr_hi, msr_lo;
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	ia32_msr_read(IA32_APIC_BASE, &msr_lo, &msr_hi);
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	msr_lo |= (1 << IA32_APIC_BASE_ENABLE_BIT);
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	ia32_msr_write(IA32_APIC_BASE, msr_lo, msr_hi);
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#endif /* LAPIC_REGS_X86_H_ */
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}
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int lapic_enable(void) {
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	uint32_t val;
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	lapic_enable_in_msr();
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    /**
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	 * Current Model is Flat Model of logical destination Mode
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	 * 0xF in DFR is Flat Model, 0x0 in DFR is cluster Model
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	 * ATTENTION: Flat Model limits the number of CPU to 8
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	 */
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	val = (0x1 << cpu_get_id()) << 24; /* logical APIC ID is specified in bit */
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	lapic_write(LAPIC_LDR, val);
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	val = (0xF << 28);
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	lapic_write(LAPIC_DFR, val);
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    /* Set the spurious interrupt vector register */
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	val = lapic_read(LAPIC_SIVR);
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	val |= 0x100;
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	lapic_write(LAPIC_SIVR, val);
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#if 0
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	/* Clear error state register */
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	lapic_errstatus();
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	lapic_write(LAPIC_LVT_TR, LAPIC_DISABLE);
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	lapic_write(LAPIC_LVT_PCR, LAPIC_NMI);
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	lapic_write(LAPIC_LVT_LINT0, LAPIC_DISABLE);
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	lapic_write(LAPIC_LVT_LINT1, LAPIC_DISABLE);
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	lapic_write(LAPIC_TASKPRIOR, 0);
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#endif
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	return 0;
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}
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PERIPH_MEMORY_DEFINE(local_apic, LOCAL_APIC_DEF_ADDR, 0x1000);
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