embox

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/**
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 * @file
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 * @brief
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 *
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 * @date 05.02.2013
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 * @author Anton Bulychev
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 */
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#include <embox/unit.h>
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#include <stdint.h>
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#include <hal/cpu.h>
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#include <asm/io.h>
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#include "lapic.h"
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#include <drivers/irqctrl.h>
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#include <drivers/common/memory.h>
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#include <module/embox/driver/interrupt/lapic.h>
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#ifdef LAPIC_REGS_X86_H_
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#include "drivers/i8259_regs.h"
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#endif
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EMBOX_UNIT_INIT(ioapic_enable);
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static inline void i8259_disable(void)
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{
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#ifdef IOAPIC_REGS_X86_H_ /* Needed only for x86 */
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	outb(0xFF, PIC2_DATA);
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	outb(0xFF, PIC1_DATA);
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	//inb(PIC1_DATA);
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#endif /* IOAPIC_REGS_X86_H_ */
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}
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/**
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 * Initialize the IOAPIC
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 */
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static int ioapic_enable(void) {
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	static int inited = 0;
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	if (inited & 0x1 << cpu_get_id()) {
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		return 0;
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	}else
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		inited |= 0x1 << cpu_get_id();
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#ifdef IOAPIC_REGS_X86_H_
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	/* I'm not sure that it is correct */
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	outb(0x70, 0x22);
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	outb(0x01, 0x23);
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#endif
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	return 0;
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}
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void apic_init(void) {
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	i8259_disable();
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	ioapic_enable();
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	lapic_enable();
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}
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static inline uint32_t irq_redir_low(unsigned int irq) {
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	uint32_t val = 0;
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	if (irq < 16) {
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		/* ISA active-high */
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		val |= IOAPIC_ICR_HIGH_POLARITY;
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		/* ISA edge triggered */
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		val |= IOAPIC_ICR_EDGE_TRIGGER;
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	}
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	else {
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		/* PCI active-low */
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		val |= IOAPIC_ICR_LOW_POLARITY;
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		/* PCI level triggered */
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		val |= IOAPIC_ICR_LEVEL_TRIGGER;
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	}
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	val |= IOAPIC_ICR_DM_FIXED;
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	val |= IOAPIC_ICR_LOGICAL_DEST;
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	val |= (irq + 0x20);
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	/* Return with Mask bit clear */
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	return val;
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}
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void irqctrl_enable(unsigned int irq) {
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	uint32_t low;
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	static uint32_t high = 0;
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	if (irq >= 24) {
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		/* msi irq */
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		return;
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	}
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	low = irq_redir_low(irq);
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	/**
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	 * In both SMP and NOSMP situation, we can use logical destination
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	 * mode to delivery interrupt. But when we add CPU in such mode,
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	 * we only need to call irqctrl_enable() at each CPUs to set bit
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	 */
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	high |= lapic_read(LAPIC_LDR);
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	ioapic_write(IOAPIC_REDIR_TABLE + irq * 2, low);
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	ioapic_write(IOAPIC_REDIR_TABLE + irq * 2 + 1, high);
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}
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void irqctrl_disable(unsigned int irq) {
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	uint32_t low;
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	if (irq == 0) {
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		/*None Maskable interrupt*/
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		return;
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	}
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	if (irq >= 24) {
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		/* msi irq */
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		return;
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	}
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	low = ioapic_read(IOAPIC_REDIR_TABLE + irq * 2);
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	low |= IOAPIC_ICR_INT_MASK;
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	ioapic_write(IOAPIC_REDIR_TABLE + irq * 2, low);
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}
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void irqctrl_force(unsigned int irq) {
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	// TODO Emm?.. -- Eldar
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}
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int irqctrl_pending(unsigned int irq) {
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	// TODO Emm?.. -- Anton
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	return 1;
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}
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void irqctrl_eoi(unsigned int irq) {
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	//TODO: irq >= 16
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	if (irq >= 24) {
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		/* msi irq */
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		return;
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	}
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	lapic_send_eoi();
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}
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IRQCTRL_DEF(iopic, NULL);
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PERIPH_MEMORY_DEFINE(iopic, IOAPIC_DEF_ADDR, 0x100);
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