embox

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/**
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 * @file
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 * @brief TWI communication for Lego AVR
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 *
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 * @date 26.09.10
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 * @author Anton Kozlov
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 * @author Fedor Burdun
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 */
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#include <stdint.h>
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#include <embox/unit.h>
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#include <kernel/panic.h>
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#include <hal/reg.h>
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#include <hal/system.h>
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#include <drivers/at91sam7s256.h>
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#include <drivers/twi.h>
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EMBOX_UNIT_INIT(twi_init);
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#define   TWICLK           400000L //TODO move to global config -- special to system where runs
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#define   CLDIV            (((SYS_CLOCK/TWICLK)/2)-3)
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static uint32_t twi_pending;
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static uint8_t *twi_ptr;
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static uint32_t twi_mask;
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#define BUF_SIZE 128
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static uint8_t out_buff[BUF_SIZE];
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static void systick_wait_ns(uint32_t ns) {
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	uint32_t x = (ns >> 7) + 1;
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	while (x) {
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		x--;
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	}
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}
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static void twi_reset(void) {
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	uint32_t clocks = 9;
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	REG_STORE(AT91C_TWI_IDR, ~0);
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	REG_STORE(AT91C_PMC_PCER, (1 << AT91C_ID_PIOA) |  /* Need PIO too */
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			(1 << AT91C_ID_TWI));    /* TWI clock domain */
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	/* MAGIC Set up pin as an IO pin for clocking till clean */
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	/* Why we need to clock? */
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	REG_STORE(AT91C_PIOA_MDER, AT91C_PA3_TWD | AT91C_PA4_TWCK);
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	REG_STORE(AT91C_PIOA_PER, AT91C_PA3_TWD | AT91C_PA4_TWCK);
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	REG_STORE(AT91C_PIOA_ODR, AT91C_PA3_TWD);
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	REG_STORE(AT91C_PIOA_OER, AT91C_PA4_TWCK);
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	while (clocks > 0 && !(REG_LOAD(AT91C_PIOA_PDSR) & AT91C_PA3_TWD)) {
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		REG_STORE(AT91C_PIOA_CODR, AT91C_PA4_TWCK);
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		systick_wait_ns(1500);
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		REG_STORE(AT91C_PIOA_SODR, AT91C_PA4_TWCK);
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		systick_wait_ns(1500);
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		clocks--;
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	}
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	REG_STORE(AT91C_PIOA_PDR, AT91C_PA3_TWD | AT91C_PA4_TWCK);
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	REG_STORE(AT91C_PIOA_ASR, AT91C_PA3_TWD | AT91C_PA4_TWCK);
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	/* MAGIC END */
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	/* Disable & reset */
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	REG_STORE(AT91C_TWI_CR, AT91C_TWI_SWRST | AT91C_TWI_MSDIS);
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	/* Set for 400kHz */
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	REG_STORE(AT91C_TWI_CWGR, ((CLDIV << 8) | CLDIV));
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	/* Enable as master */
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	REG_STORE(AT91C_TWI_CR, AT91C_TWI_MSEN);
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	//*AT91C_TWI_IER = AT91C_TWI_NACK;
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	twi_mask = 0;
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}
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static int twi_init(void) {
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	twi_reset();
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	return 0;
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}
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void twi_write(uint32_t dev_addr, const uint8_t *data, uint32_t nBytes) {
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	twi_ptr = (uint8_t *) data;
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	twi_pending = nBytes;
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	REG_STORE(AT91C_TWI_MMR, AT91C_TWI_IADRSZ_NO | ((dev_addr & 0x7f) << 16));
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	REG_STORE(AT91C_TWI_THR, *twi_ptr++);
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	twi_pending--;
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	while (twi_pending > 0) {
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		while (!(REG_LOAD(AT91C_TWI_SR) & AT91C_TWI_TXRDY));
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		REG_STORE(AT91C_TWI_THR, *twi_ptr++);
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		twi_pending--;
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	}
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	while (!(REG_LOAD(AT91C_TWI_SR) & AT91C_TWI_TXCOMP));
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}
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void twi_send(uint32_t dev_addr, const uint8_t *data, uint32_t count) {
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	const uint8_t *sptr = data;
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	uint8_t *dptr = out_buff;
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	uint8_t checkbyte = 0;
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	uint32_t left_count = count;
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#if 0
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	if (count >= BUF_SIZE) {
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		panic("Sending to AVR abnormal long data\n");
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	}
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#endif
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	while (left_count-- > 0) {
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		checkbyte += *sptr;
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		*dptr++ = *sptr++;
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	}
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	*dptr = ~checkbyte;
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	twi_write(dev_addr, out_buff, count + 1);
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}
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int twi_receive(uint32_t dev_addr, uint8_t *data, uint32_t count) {
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	uint8_t *ptr = data;
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	uint8_t checkbyte = 0;
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	REG_STORE(AT91C_TWI_MMR, AT91C_TWI_IADRSZ_NO |
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			AT91C_TWI_MREAD | ((dev_addr & 0x7f) << 16));
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	REG_STORE(AT91C_TWI_CR, AT91C_TWI_START);
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	while (count-- > 1) {
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		while (!(REG_LOAD(AT91C_TWI_SR) & AT91C_TWI_RXRDY));
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		*ptr = REG_LOAD(AT91C_TWI_RHR);
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		checkbyte += *ptr;
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		ptr++;
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	}
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	REG_STORE(AT91C_TWI_CR, AT91C_TWI_STOP);
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	while (!(REG_LOAD(AT91C_TWI_SR) & AT91C_TWI_RXRDY)) {
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	}
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	*ptr = REG_LOAD(AT91C_TWI_RHR);
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	checkbyte += *ptr;
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	while (!(REG_LOAD(AT91C_TWI_SR) & AT91C_TWI_TXCOMP)) {
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	}
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	return ((checkbyte == 0xff) ? 1 : 0);
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}
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