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embox
/src
/drivers
/gpu
/ipu_v3
/
ipuv3.c 
275 строк · 7.5 Кб
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/**
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 * @file ipuv3.c
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 * @brief Probe/irq handle/reset/channel init/etc
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 * @date Sep 15, 2017
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 * @author Anton Bondarev
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 */
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#include <util/log.h>
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#include <string.h>
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#include <assert.h>
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#include <hal/reg.h>
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#include <drivers/common/memory.h>
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#include <drivers/video/fb.h>
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#include <drivers/clk/ccm_imx6.h>
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#include <kernel/irq.h>
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#include "ipu_regs.h"
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#include "ipu_priv.h"
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#include "ipu_param_mem.h"
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extern void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt);
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extern void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan);
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extern void _ipu_init_dc_mappings(struct ipu_soc *ipu);
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extern void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel);
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static struct ipu_soc ipu_soc;
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#define idma_mask(ch)		(1UL << (ch & 0x1F))
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#define idma_is_set(ipu, reg, dma)	(ipu_idmac_read(ipu, reg(dma)) & idma_mask(dma))
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/**
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 * @brief Perform software reset for all IPU modules
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 */
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static void ipu_reset(void) {
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#define SRC_BASE 0x20D8000
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# define SRC_IPU_RESET (1 << 3)
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	REG32_ORIN(SRC_BASE, SRC_IPU_RESET);
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	int timeout=0xfffff;
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	while(timeout--) {
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		if (!(REG32_LOAD(SRC_BASE) & SRC_IPU_RESET)) {
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			break;
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		}
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	}
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	if (timeout == 0) {
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		log_error("IPU reset timeout!\n");
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	} else {
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		log_debug("IPU reset ok!\n");
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	}
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}
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static int ipu_mem_reset(struct ipu_soc *ipu) {
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	int i = 1000000;
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	ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
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	while (i-- > 0) {
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		if (!(ipu_cm_read(ipu, IPU_MEM_RST) & (1u << 31)))
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			break;
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	}
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	if (i <= 0) {
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		log_error("Failed to reset IPU internal memories");
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	}
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	return 0;
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}
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struct ipu_soc *ipu_get() {
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	return &ipu_soc;
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}
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int ipu_probe(void) {
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	struct ipu_soc *ipu = ipu_get();
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	clk_enable("ipu1");
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	memset(ipu, 0, sizeof(struct ipu_soc));
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	ipu->cm_reg		= (void*) IPU_BASE + IPU_CM_REG_BASE;
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	ipu->ic_reg		= (void*) IPU_BASE + IPU_IC_REG_BASE;
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	ipu->idmac_reg		= (void*) IPU_BASE + IPU_IDMAC_REG_BASE;
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	ipu->dp_reg		= (void*) IPU_BASE + IPU_SRM_REG_BASE;
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	ipu->dc_reg		= (void*) IPU_BASE + IPU_DC_REG_BASE;
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	ipu->dmfc_reg		= (void*) IPU_BASE + IPU_DMFC_REG_BASE;
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	ipu->di_reg[0]		= (void*) IPU_BASE + IPU_DI0_REG_BASE;
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	ipu->di_reg[1]		= (void*) IPU_BASE + IPU_DI1_REG_BASE;
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	ipu->smfc_reg		= (void*) IPU_BASE + IPU_SMFC_REG_BASE;
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	ipu->cpmem_base		= (void*) IPU_BASE + IPU_CPMEM_REG_BASE;
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	ipu->tpmem_base		= (void*) IPU_BASE + IPU_TPM_REG_BASE;
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	ipu->dc_tmpl_reg	= (void*) IPU_BASE + IPU_DC_TMPL_REG_BASE;
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	ipu->vdi_reg		= (void*) IPU_BASE + IPU_VDI_REG_BASE;
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	ipu->disp_base[1]	= (void*) IPU_BASE + IPU_DISP1_BASE;
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	ipu_reset();
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	/* Disable all channels */
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	ipu_idmac_write(ipu, 0x0, IDMAC_WM_EN(0));
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	ipu_idmac_write(ipu, 0x0, IDMAC_WM_EN(32));
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	ipu_idmac_write(ipu, 0x0, IDMAC_WM_EN(0));
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	ipu_idmac_write(ipu, 0x0, IDMAC_WM_EN(32));
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_CHA_CUR_BUF(0));
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_CHA_CUR_BUF(32));
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	ipu_cm_write(ipu, 0x0, IPU_CHA_DB_MODE_SEL(0));
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	ipu_cm_write(ipu, 0x0, IPU_CHA_DB_MODE_SEL(32));
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	memset((void*) ipu->cpmem_base, 0, IPU_CPMEM_REG_LEN);
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	clk_enable("ipu1");
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	clk_enable("ipu1_di0");
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	clk_enable("ldb_di0");
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	ipu_mem_reset(ipu);
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	_ipu_init_dc_mappings(ipu);
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	/* Enable error interrupts by default */
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
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	return 0;
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}
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int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params) {
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	/* note: assume channel is MEM_BG_SYNC
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	 *       assume DI=0			*/
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	log_debug("init channel = %d", IPU_CHAN_VIDEO_IN_DMA(channel));
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	/* Re-enable error interrupts every time a channel is initialized */
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
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	ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
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	ipu->dc_di_assignment[5] = 0;
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	_ipu_dc_init(ipu, 5, 0, 0, IPU_PIX_FMT_RGB666);
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	return 0;
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}
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void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel) {
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	uint32_t ipu_conf;
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	_ipu_dc_uninit(ipu, 5);
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	ipu_conf = ipu_cm_read(ipu, IPU_CONF);
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	ipu_conf &= ~IPU_CONF_DC_EN;
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	ipu_conf &= ~IPU_CONF_DP_EN;
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	ipu_conf &= ~IPU_CONF_DMFC_EN;
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	ipu_conf &= ~IPU_CONF_DI0_EN;
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	ipu_cm_write(ipu, ipu_conf, IPU_CONF);
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}
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int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
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				ipu_buffer_t type,
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				uint32_t pixel_fmt,
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				uint16_t width, uint16_t height,
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				uint32_t stride,
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				dma_addr_t phyaddr_0) {
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	uint32_t dma_chan = IPU_CHAN_VIDEO_IN_DMA(channel);
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	assert(dma_chan == 23); /* XXX */
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	_ipu_ch_param_init(ipu, dma_chan, pixel_fmt, width, height, stride, 0, 0, 0,
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			   phyaddr_0);
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	return 0;
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}
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int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel) {
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	uint32_t reg;
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	uint32_t ipu_conf;
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	uint32_t in_dma = IPU_CHAN_VIDEO_IN_DMA(channel);
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	assert(in_dma == 23); /* XXX */
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	ipu_conf = IPU_CONF_DP_EN | IPU_CONF_DC_EN | IPU_CONF_DMFC_EN;
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	ipu_conf |= IPU_CONF_DI0_EN;
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	ipu_cm_write(ipu, ipu_conf, IPU_CONF);
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	reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
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	ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
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	reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
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	ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
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	_ipu_dp_dc_enable(ipu, channel);
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	ipu_cm_write(ipu, 0x1400000, IPU_DISP_GEN);
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	return 0;
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}
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void _ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
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		uint32_t bufNum) {
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	uint32_t dma_ch = IPU_CHAN_VIDEO_IN_DMA(channel);
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	assert(dma_ch == 23); /* XXX */
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	ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
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	ipu_cm_write(ipu, idma_mask(dma_ch), IPU_CHA_BUF0_RDY(dma_ch));
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	ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
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}
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void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
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		uint32_t bufNum) {
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	_ipu_clear_buffer_ready(ipu, channel, type, bufNum);
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}
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int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop) {
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	uint32_t reg;
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	uint32_t in_dma = IPU_CHAN_VIDEO_IN_DMA(channel);
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	assert(in_dma == 23); /* XXX */
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	reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
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	ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
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	reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
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	ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
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	ipu_cm_write(ipu, idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
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	_ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 0);
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	return 0;
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}
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void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq) {
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	uint32_t reg;
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	reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
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	reg &= ~IPUIRQ_2_MASK(irq);
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	ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
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}
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void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq) {
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	ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
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}
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int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
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		    /* irq_return_t(*handler) (int, void *), */
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		    uint32_t irq_flags, const char *devname, void *dev_id) {
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	uint32_t reg;
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	ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
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	reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
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	reg |= IPUIRQ_2_MASK(irq);
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	ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
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	return 0;
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}
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void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id) {
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	uint32_t reg;
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	reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
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	reg &= ~IPUIRQ_2_MASK(irq);
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	ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
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}
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PERIPH_MEMORY_DEFINE(ipu, IPU_BASE, 0x200000);
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#define DCIC1_BASE 0x20E4000
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#define DCIC2_BASE 0x20E8000
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PERIPH_MEMORY_DEFINE(ipu_dcic1, DCIC1_BASE, 0x20);
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PERIPH_MEMORY_DEFINE(ipu_dcic2, DCIC2_BASE, 0x20);
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PERIPH_MEMORY_DEFINE(ipu_src, SRC_BASE, 0x4);
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