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embox
/src
/drivers
/gpu
/ipu_v3
/
ipu_disp.c 
331 строка · 9.8 Кб
1
/**
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 * @file ipu_disp.c
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 * @brief Configure channels, waves etc
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 * @author Denis Deryugin <deryugin.denis@gmail.com>
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 * @version
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 * @date 28.08.2018
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 */
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#include <util/log.h>
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#include <errno.h>
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#include <stdint.h>
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#include <drivers/lvds/imx/ldb.h>
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#include <drivers/clk/ccm_imx6.h>
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#include <drivers/video/fb.h>
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#include "ipu_regs.h"
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#include "ipu_priv.h"
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#define SYNC_WAVE 0
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#define NULL_WAVE (-1)
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#define DC_DISP_ID_SYNC(di)	(di)
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static void _ipu_di_data_wave_config(struct ipu_soc *ipu,
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				int di, int wave_gen,
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				int access_size, int component_size)
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{
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	uint32_t reg;
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	reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
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	    (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
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	ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
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}
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static void _ipu_di_data_pin_config(struct ipu_soc *ipu,
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			int di, int wave_gen, int di_pin, int set,
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			int up, int down)
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{
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	uint32_t reg;
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	reg = ipu_di_read(ipu, di, DI_DW_GEN(wave_gen));
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	reg &= ~(0x3 << (di_pin * 2));
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	reg |= set << (di_pin * 2);
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	ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
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	ipu_di_write(ipu, di, (down << 16) | up, DI_DW_SET(wave_gen, set));
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}
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static void _ipu_di_sync_config(struct ipu_soc *ipu,
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				int di, int wave_gen,
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				int run_count, int run_src,
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				int offset_count, int offset_src,
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				int repeat_count, int cnt_clr_src,
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				int cnt_polarity_gen_en,
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				int cnt_polarity_clr_src,
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				int cnt_polarity_trigger_src,
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				int cnt_up, int cnt_down)
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{
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	uint32_t reg;
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	reg = (run_count << 19) | (++run_src << 16) |
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	    (offset_count << 3) | ++offset_src;
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	ipu_di_write(ipu, di, reg, DI_SW_GEN0(wave_gen));
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	reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
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	    (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
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	reg |= (cnt_down << 16) | cnt_up;
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	if (repeat_count == 0) {
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		/* Enable auto reload */
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		reg |= 0x10000000;
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	}
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	ipu_di_write(ipu, di, reg, DI_SW_GEN1(wave_gen));
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	reg = ipu_di_read(ipu, di, DI_STP_REP(wave_gen));
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	reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
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	reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
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	ipu_di_write(ipu, di, reg, DI_STP_REP(wave_gen));
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}
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static void _ipu_dc_map_config(struct ipu_soc *ipu,
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		int map, int byte_num, int offset, int mask)
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{
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	log_debug("Enter %s", __func__);
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	int ptr = map * 3 + byte_num;
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	uint32_t reg;
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	reg = ipu_dc_read(ipu, DC_MAP_CONF_VAL(ptr));
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	reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
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	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
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	ipu_dc_write(ipu, reg, DC_MAP_CONF_VAL(ptr));
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	reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
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	reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
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	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
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	ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(map));
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}
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static void _ipu_dc_map_clear(struct ipu_soc *ipu, int map)
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{
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	log_debug("Enter %s", __func__);
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	uint32_t reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
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	ipu_dc_write(ipu, reg & ~(0xFFFF << (16 * (map & 0x1))),
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		     DC_MAP_CONF_PTR(map));
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}
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static void _ipu_dc_write_tmpl(struct ipu_soc *ipu,
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			int word, uint32_t opcode, uint32_t operand, int map,
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			int wave, int glue, int sync, int stop)
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{
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	log_debug("Enter %s", __func__);
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	uint32_t reg;
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	if (opcode == WRG) {
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		reg = sync;
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		reg |= (glue << 4);
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		reg |= (++wave << 11);
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		reg |= ((operand & 0x1FFFF) << 15);
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		ipu_dc_tmpl_write(ipu, reg, word * 8);
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		reg = (operand >> 17);
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		reg |= opcode << 7;
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		reg |= (stop << 9);
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		ipu_dc_tmpl_write(ipu, reg, word * 8 + 4);
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	} else {
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		reg = sync;
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		reg |= (glue << 4);
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		reg |= (++wave << 11);
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		reg |= (++map << 15);
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		reg |= (operand << 20) & 0xFFF00000;
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		ipu_dc_tmpl_write(ipu, reg, word * 8);
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		reg = (operand >> 12);
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		reg |= opcode << 4;
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		reg |= (stop << 9);
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		ipu_dc_tmpl_write(ipu, reg, word * 8 + 4);
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	}
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	log_debug("Exit %s", __func__);
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}
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static void _ipu_dc_link_event(struct ipu_soc *ipu,
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		int chan, int event, int addr, int priority)
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{
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	uint32_t reg;
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	reg = ipu_dc_read(ipu, DC_RL_CH(chan, event));
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	reg &= ~(0xFFFF << (16 * (event & 0x1)));
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	reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
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	ipu_dc_write(ipu, reg, DC_RL_CH(chan, event));
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}
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void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
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{
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	log_debug("enter %s, dc_chan=%d, di=%d\n", __func__, dc_chan, di);
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	uint32_t reg;
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 5, 3);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 6, 2);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 12, 1);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
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	reg = 0x2;
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	reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
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	reg |= di << 2;
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	ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
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	ipu_dc_write(ipu, 0x00000000, DC_WR_CH_ADDR(dc_chan));
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	ipu_dc_write(ipu, 0x00000084, DC_GEN);
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}
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void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan)
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{
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
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	_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
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}
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void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel)
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{
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	uint32_t reg;
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	uint32_t dc_chan = 5;
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	reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
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	ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
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	reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
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	reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
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	ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
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	clk_enable("ipu1_di0");
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}
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enum {
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	IPU_RGB24_MAP = 0,
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	IPU_RGB565_MAP = 1,
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};
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void _ipu_init_dc_mappings(struct ipu_soc *ipu) {
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	/* Configure maps (used in ipu_init_sync_panel)
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	 *
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	 * Configuration is done in the following way:
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	 *	_ipu_dc_map_config(ipu, MAP, COLOR, OFFSET, CONST)
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	 *
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	 *	last const is currently unknown
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	 *
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	 *	MAP is just a number 0 ... 5
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	 *
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	 *	COLOR is: 0 for RED
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	 *	          1 for GREEN
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	 *	          2 for BLUE
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	 *
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	 *	OFFSET is the highest bit of the color
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	 * */
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	/* RGB24 */
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	_ipu_dc_map_clear(ipu, IPU_RGB24_MAP);
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	_ipu_dc_map_config(ipu, IPU_RGB24_MAP, 0, 7, 0xFF);
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	_ipu_dc_map_config(ipu, IPU_RGB24_MAP, 1, 15, 0xFF);
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	_ipu_dc_map_config(ipu, IPU_RGB24_MAP, 2, 23, 0xFF);
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	/* RGB565 */
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	_ipu_dc_map_clear(ipu, IPU_RGB565_MAP);
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	_ipu_dc_map_config(ipu, IPU_RGB565_MAP, 0, 5, 0xFC);
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	_ipu_dc_map_config(ipu, IPU_RGB565_MAP, 1, 11, 0xFC);
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	_ipu_dc_map_config(ipu, IPU_RGB565_MAP, 2, 17, 0xFC);
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}
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int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp,
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			    struct fb_info *fbi,
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			    uint32_t pixel_fmt) {
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	uint16_t width = fbi->var.xres;
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	uint16_t height = fbi->var.yres;
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	uint16_t h_start_width = fbi->var.left_margin;
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	uint16_t h_sync_width = fbi->var.hsync_len;
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	uint16_t h_end_width = fbi->var.right_margin;
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	uint16_t v_start_width = fbi->var.upper_margin;
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	uint16_t v_sync_width = fbi->var.vsync_len;
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	uint16_t v_end_width = fbi->var.lower_margin;
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	uint32_t reg;
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	uint32_t di_gen;
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	uint32_t div;
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	uint32_t h_total, v_total;
252
	int map;
253


254
	if ((v_sync_width == 0) || (h_sync_width == 0))
255
		return -EINVAL;
256


257
	if (v_end_width < 2) {
258
		v_end_width = 2;
259
		log_debug("Adjusted v_end_width");
260
	}
261


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	h_total = width + h_sync_width + h_start_width + h_end_width;
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	v_total = height + v_sync_width + v_start_width + v_end_width;
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	/* try ipu clk first*/
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	ipu_di_write(ipu, disp, 3 << 20, DI_GENERAL);
267


268
	div = 1;
269


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	ipu_di_write(ipu, 0, div << 4, DI_BS_CLKGEN0);
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	ipu_di_write(ipu, 0, div << 16, DI_BS_CLKGEN1);
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	_ipu_di_data_wave_config(ipu, disp, SYNC_WAVE, div - 1, div - 1);
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	_ipu_di_data_pin_config(ipu, disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
275


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	/* XXX hardcoded for use with LVDS */
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	if (ldb_bits() == 18) {
278
		map = IPU_RGB565_MAP;
279
	} else { /* Assume 24 bits */
280
		map = IPU_RGB24_MAP;
281
	}
282


283
	/*clear DI*/
284
	di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
285
	di_gen &= (0x3 << 20);
286
	ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
287
	/* Setup internal HSYNC waveform */
288
	_ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
289
				0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
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				DI_SYNC_NONE, 0, 0);
291
	/* Setup external (delayed) HSYNC waveform */
292
	_ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1,
293
			    DI_SYNC_CLK, div * 0, DI_SYNC_CLK,
294
			    0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
295
			    DI_SYNC_CLK, 0, h_sync_width * 2);
296
	/* Setup VSYNC waveform */
297
	_ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1,
298
			    DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
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			    DI_SYNC_NONE, 1, DI_SYNC_NONE,
300
			    DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
301
	ipu_di_write(ipu, disp, v_total - 1, DI_SCR_CONF);
302


303
	/* Setup active data waveform to sync with DC */
304
	_ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_HSYNC,
305
			    v_sync_width + v_start_width, DI_SYNC_HSYNC, height,
306
			    DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
307
			    DI_SYNC_NONE, 0, 0);
308
	_ipu_di_sync_config(ipu, disp, 5, 0, DI_SYNC_CLK,
309
			    h_sync_width + h_start_width, DI_SYNC_CLK,
310
			    width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
311


312
	_ipu_dc_write_tmpl(ipu, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
313
	_ipu_dc_write_tmpl(ipu, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
314
	_ipu_dc_write_tmpl(ipu, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
315
	_ipu_dc_write_tmpl(ipu, 12, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
316


317
	di_gen |= DI_GEN_POLARITY_DISP_CLK;
318
	di_gen |= (1 << 20);
319
	ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
320


321
	ipu_di_write(ipu, disp, (DI_SYNC_HSYNC << DI_VSYNC_SEL_OFFSET) |
322
			0x00000002, DI_SYNC_AS_GEN);
323
	reg = ipu_di_read(ipu, disp, DI_POL);
324
	reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
325
	reg |= DI_POL_DRDY_POLARITY_15;
326
	ipu_di_write(ipu, disp, reg, DI_POL);
327


328
	ipu_dc_write(ipu, width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
329


330
	return 0;
331
}
332

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