embox

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/*
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 * Copyright (C) 2016 Etnaviv Project
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  *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 as published by
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 * the Free Software Foundation.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License along with
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 * this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#include <asm-generic/dma-mapping.h>
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#include "etnaviv_compat.h"
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_gpu.h"
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#include "etnaviv_mmu.h"
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#include "etnaviv_drv.h"
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#include "etnaviv_iommu.h"
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#include <etnaviv_xml/state.xml.h>
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#include <etnaviv_xml/state_hi.xml.h>
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#define MMUv2_PTE_PRESENT		BIT(0)
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#define MMUv2_PTE_EXCEPTION		BIT(1)
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#define MMUv2_PTE_WRITEABLE		BIT(2)
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#define MMUv2_MTLB_MASK			0xffc00000
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#define MMUv2_MTLB_SHIFT		22
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#define MMUv2_STLB_MASK			0x003ff000
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#define MMUv2_STLB_SHIFT		12
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#define MMUv2_MAX_STLB_ENTRIES		1024
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static int etnaviv_iommuv2_init(struct etnaviv_gpu *gpu) {
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	uint32_t *p;
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	int ret, i, j;
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	struct etnaviv_iommuv2_domain *etnaviv_domain = (void*) gpu->mmu.domain;
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	/* allocate scratch page */
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	etnaviv_domain->bad_page_cpu = dma_alloc_coherent(etnaviv_domain->dev,
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						  SZ_4K,
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						  &etnaviv_domain->bad_page_dma,
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						  GFP_KERNEL);
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	if (!etnaviv_domain->bad_page_cpu) {
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		ret = -ENOMEM;
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		goto fail_mem;
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	}
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	p = etnaviv_domain->bad_page_cpu;
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	for (i = 0; i < SZ_4K / 4; i++)
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		*p++ = 0xdead55aa;
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	etnaviv_domain->mtlb_cpu = dma_alloc_coherent(etnaviv_domain->dev,
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						  SZ_4K,
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						  &etnaviv_domain->mtlb_dma,
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						  GFP_KERNEL);
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	if (!etnaviv_domain->mtlb_cpu) {
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		ret = -ENOMEM;
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		goto fail_mem;
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	}
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	/* pre-populate STLB pages (may want to switch to on-demand later) */
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	for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
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		etnaviv_domain->stlb_cpu[i] =
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				dma_alloc_coherent(etnaviv_domain->dev,
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						   SZ_4K,
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						   &etnaviv_domain->stlb_dma[i],
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						   GFP_KERNEL);
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		if (!etnaviv_domain->stlb_cpu[i]) {
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			ret = -ENOMEM;
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			goto fail_mem;
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		}
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		p = etnaviv_domain->stlb_cpu[i];
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		for (j = 0; j < SZ_4K / 4; j++)
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			*p++ = MMUv2_PTE_EXCEPTION;
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		etnaviv_domain->mtlb_cpu[i] = etnaviv_domain->stlb_dma[i] |
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					      MMUv2_PTE_PRESENT;
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	}
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	return 0;
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fail_mem:
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	if (etnaviv_domain->bad_page_cpu)
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		dma_free_coherent(etnaviv_domain->dev, SZ_4K,
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				  etnaviv_domain->bad_page_cpu,
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				  etnaviv_domain->bad_page_dma);
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	if (etnaviv_domain->mtlb_cpu)
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		dma_free_coherent(etnaviv_domain->dev, SZ_4K,
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				  etnaviv_domain->mtlb_cpu,
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				  etnaviv_domain->mtlb_dma);
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	for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
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		if (etnaviv_domain->stlb_cpu[i])
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			dma_free_coherent(etnaviv_domain->dev, SZ_4K,
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					  etnaviv_domain->stlb_cpu[i],
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					  etnaviv_domain->stlb_dma[i]);
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	}
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	return ret;
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}
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void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu) {
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	struct etnaviv_iommuv2_domain *etnaviv_domain = (void *) gpu->mmu.domain;
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	uint16_t prefetch;
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	/* If the MMU is already enabled the state is still there. */
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	if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE)
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		return;
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	prefetch = etnaviv_buffer_config_mmuv2(gpu,
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				(uint32_t)etnaviv_domain->mtlb_dma,
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				(uint32_t)etnaviv_domain->bad_page_dma);
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	etnaviv_gpu_start_fe(gpu, (uint32_t)etnaviv_cmdbuf_get_pa(gpu->buffer),
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			     prefetch);
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	etnaviv_gpu_wait_idle(gpu, 100);
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	gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE);
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}
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int etnaviv_iommuv2_domain_init(struct etnaviv_gpu *gpu) {
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	gpu->mmu.start_addr = 0;
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	gpu->mmu.end_addr = 4096 - 1;
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	memset(gpu->mmu.domain, 0, sizeof(struct etnaviv_iommuv2_domain));
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	if (etnaviv_iommuv2_init(gpu)) {
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		return -1;
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	}
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	return 0;
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}
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