embox

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/**
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 * @file
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 * @brief Direct Rendering Manager compatibility module
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 * @author Denis Deryugin <deryugin.denis@gmail.com>
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 * @version
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 * @date 06.12.2017
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 */
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#include <drm.h>
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#include <errno.h>
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#include <etnaviv_drm.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <sys/stat.h>
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#include <sys/uio.h>
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#include <drivers/char_dev.h>
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#include <drivers/clk/ccm_imx6.h>
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#include <drivers/common/memory.h>
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#include <drivers/power/imx.h>
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#include <embox_drm/drm_gem.h>
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#include <embox_drm/drm_priv.h>
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#include <etnaviv_xml/common.xml.h>
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#include <etnaviv_xml/state_hi.xml.h>
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#include <fs/dvfs.h>
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#include <hal/cache.h>
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#include <kernel/irq.h>
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#include <mem/vmem.h>
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#include <util/err.h>
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#include <util/log.h>
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#include <util/macro.h>
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#include "etnaviv_drv.h"
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#include "etnaviv_gem.h"
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#include "etnaviv_gpu.h"
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#define VERSION_NAME            "etnaviv"
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#define VERSION_NAME_LEN        9
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#define VERSION_DATE            "7 Dec 2017"
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#define VERSION_DATE_LEN        10
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#define VERSION_DESC            "DEADBEEF"
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#define VERSION_DESC_LEN        8
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/* Interrupt numbers */
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#define GPU3D_IRQ               OPTION_GET(NUMBER, gpu3d_irq)
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#define R2D_GPU2D_IRQ           OPTION_GET(NUMBER, r2d_gpu2d_irq)
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#define V2D_GPU2D_IRQ           OPTION_GET(NUMBER, v2d_gpu2d_irq)
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#define ETNA_UNCACHED_BUFFER_SZ (16 * 1024 * 1024)
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static uint8_t etnaviv_uncached_buffer[ETNA_UNCACHED_BUFFER_SZ]
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    __attribute__((aligned(0x1000)));
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/*
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 * DRM ioctls:
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 */
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static const char *drm_call_to_string[] = {
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    [0x00] = "GET_PARAM   ",
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    [0x01] = "SET_PARAM   ",
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    [0x02] = "GEM_NEW     ",
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    [0x03] = "GEM_INFO    ",
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    [0x04] = "GEM_CPU_PREP",
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    [0x05] = "GEM_CPU_FINI",
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    [0x06] = "GEM_SUBMIT  ",
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    [0x07] = "WAIT_FENCE  ",
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    [0x08] = "GEM_USERPTR ",
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    [0x09] = "GEM_WAIT    ",
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    [0x0a] = "NUM_IOCTLS  ",
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};
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int etnaviv_ioctl_gem_new(struct drm_device *dev, void *data,
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    struct drm_file *file) {
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	struct drm_etnaviv_gem_new *args = data;
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	if (args->flags
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	    & ~(ETNA_BO_CACHED | ETNA_BO_WC | ETNA_BO_UNCACHED
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	        | ETNA_BO_FORCE_MMU)) {
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		log_error("unsupported flags");
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	}
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	return etnaviv_gem_new_handle(dev, file, args->size, args->flags,
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	    (void *)&args->handle);
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}
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int etnaviv_ioctl_gem_info(struct drm_device *dev, void *data,
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    struct drm_file *file) {
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	struct drm_etnaviv_gem_info *args = data;
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	struct drm_gem_object *obj;
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	int ret;
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	if (args->pad)
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		return -EINVAL;
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	obj = drm_gem_object_lookup(file, args->handle);
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	if (!obj) {
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		log_error("obj (%p) didn't found", args->handle);
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		return -ENOENT;
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	}
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	log_debug("obj (%p) founded by handle (%i)", obj, args->handle);
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	ret = etnaviv_gem_mmap_offset(obj, &args->offset);
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	return ret;
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}
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static int etnaviv_ioctl_wait_fence(struct drm_device *dev, void *data,
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    struct drm_file *file) {
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	struct drm_etnaviv_wait_fence *args = data;
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	struct etnaviv_drm_private *priv = dev->dev_private;
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	struct etnaviv_gpu *gpu;
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	if (args->flags & ~(ETNA_WAIT_NONBLOCK))
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		return -EINVAL;
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	if (args->pipe >= ETNA_MAX_PIPES)
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		return -EINVAL;
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	gpu = priv->gpu[args->pipe];
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	if (!gpu)
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		return -ENXIO;
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	return 0;
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}
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static struct drm_device etnaviv_drm_device;
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static struct drm_file etnaviv_drm_file;
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static struct etnaviv_drm_private etnaviv_drm_private;
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static struct etnaviv_gpu etnaviv_gpus[ETNA_MAX_PIPES];
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#define VIVANTE_2D_BASE OPTION_GET(NUMBER, vivante_2d_base)
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#define VIVANTE_3D_BASE OPTION_GET(NUMBER, vivante_3d_base)
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static irq_return_t etna_irq_handler(unsigned int irq, void *data) {
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	struct etnaviv_gpu *gpu = data;
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	irq_return_t ret = IRQ_NONE;
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	int noerr = 1;
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	uint32_t intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
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	if (intr != 0) {
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		log_debug("intr 0x%08x", intr);
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		gpu->busy = 0;
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		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
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			uint32_t axi_status = gpu_read(gpu, VIVS_HI_AXI_STATUS);
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			gpu_write(gpu, VIVS_HI_INTR_ACKNOWLEDGE,
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			    VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR);
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			log_error("AXI bus error");
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			log_debug("AXI config: %08x", gpu_read(gpu, VIVS_HI_AXI_CONFIG));
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			log_debug("AXI status: %08x", axi_status);
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			if (axi_status & VIVS_HI_AXI_STATUS_DET_WR_ERR) {
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				log_error("AXI bus write error ID =0x%x",
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				    VIVS_HI_AXI_STATUS_WR_ERR_ID(axi_status));
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			}
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			if (axi_status & VIVS_HI_AXI_STATUS_DET_RD_ERR) {
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				log_error("AXI bus read error ID  =0x%x",
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				    VIVS_HI_AXI_STATUS_RD_ERR_ID(axi_status));
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			}
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			noerr = 0;
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		}
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		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
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			int i;
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			log_error("MMU fault status 0x%08x",
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			    gpu_read(gpu, VIVS_MMUv2_STATUS));
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			for (i = 0; i < 4; i++) {
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				log_error("MMU %d fault addr 0x%08x\n", i,
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				    gpu_read(gpu, VIVS_MMUv2_EXCEPTION_ADDR(i)));
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			}
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			gpu_write(gpu, VIVS_HI_INTR_ACKNOWLEDGE,
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			    VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION);
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			noerr = 0;
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		}
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		if (noerr) {
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			log_debug("no error");
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		}
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		ret = IRQ_HANDLED;
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	}
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	return ret;
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}
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static int etnaviv_dev_open(struct char_dev *cdev, struct idesc *idesc) {
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	int err;
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	int i;
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	etnaviv_drm_device.dev_private = &etnaviv_drm_private;
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	for (i = 0; i < ETNA_MAX_PIPES; i++) {
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		etnaviv_drm_private.gpu[i] = &etnaviv_gpus[i];
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	}
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	etnaviv_gpus[PIPE_ID_PIPE_2D].mmio = (void *)VIVANTE_2D_BASE;
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	etnaviv_gpus[PIPE_ID_PIPE_3D].mmio = (void *)VIVANTE_3D_BASE;
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	clk_enable("openvg");
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	clk_enable("gpu3d");
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	clk_enable("gpu2d");
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	clk_enable("vpu");
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	imx_gpu_power_set(1);
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	etnaviv_gpu_init(&etnaviv_gpus[PIPE_ID_PIPE_2D]);
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	etnaviv_gpu_debugfs(&etnaviv_gpus[PIPE_ID_PIPE_2D], "GPU2D");
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	etnaviv_gpu_init(&etnaviv_gpus[PIPE_ID_PIPE_3D]);
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	etnaviv_gpu_debugfs(&etnaviv_gpus[PIPE_ID_PIPE_2D], "GPU3D");
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	if (irq_attach(GPU3D_IRQ, etna_irq_handler, 0,
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	        &etnaviv_gpus[PIPE_ID_PIPE_3D], "i.MX6 GPU3D")) {
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		return -1;
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	}
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	if (irq_attach(R2D_GPU2D_IRQ, etna_irq_handler, 0,
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	        &etnaviv_gpus[PIPE_ID_PIPE_2D], "i.MX6 GPU2D")) {
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		return -1;
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	}
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	if (irq_attach(V2D_GPU2D_IRQ, etna_irq_handler, 0,
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	        &etnaviv_gpus[PIPE_ID_PIPE_2D], "i.MX6 GPU2D")) {
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		return -1;
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	}
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	if ((err = vmem_set_flags(vmem_current_context(),
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	         (mmu_vaddr_t)etnaviv_uncached_buffer,
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	         sizeof(etnaviv_uncached_buffer),
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	         PROT_WRITE | PROT_READ | PROT_NOCACHE))) {
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		log_error("Failed to set page attributes! Error %d", err);
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		return -1;
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	}
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	mmu_flush_tlb();
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	dcache_flush(etnaviv_uncached_buffer, sizeof(etnaviv_uncached_buffer));
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	return 0;
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}
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static void etnaviv_dev_close(struct char_dev *cdev) {
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	if (irq_detach(GPU3D_IRQ, &etnaviv_gpus[PIPE_ID_PIPE_3D])) {
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		log_error("Failed to detach GPU3D_IRQ");
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	}
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	if (irq_detach(R2D_GPU2D_IRQ, &etnaviv_gpus[PIPE_ID_PIPE_2D])) {
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		log_error("Failed to detach R2D_GPU2D_IRQ");
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	}
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	if (irq_detach(V2D_GPU2D_IRQ, &etnaviv_gpus[PIPE_ID_PIPE_2D])) {
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		log_error("Failed to detach V2D_GPU2D_IRQ");
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	}
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	imx_gpu_power_set(0);
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}
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int etnaviv_dmp(int id) {
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	assert(id >= 0 && id < ETNA_MAX_PIPES);
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	etnaviv_gpu_debugfs(&etnaviv_gpus[id],
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	    id == PIPE_ID_PIPE_2D ? "GPU2D" : "GPU3D");
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	return 0;
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}
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static int etnaviv_dev_idesc_ioctl(struct char_dev *cdev, int request,
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    void *data) {
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	drm_version_t *version;
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	int nr = _IOC_NR(request);
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	struct drm_device *dev = &etnaviv_drm_device;
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	struct drm_file *file = &etnaviv_drm_file;
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	struct drm_etnaviv_param *args = data;
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	int res = 0;
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	int pipe = args->pipe;
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	log_debug("pipe=%cD, dir=%d, type=%d, nr=%d (%s)",
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	    args->pipe == PIPE_ID_PIPE_2D ? '2' : '3', _IOC_DIR(request),
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	    _IOC_TYPE(request), _IOC_NR(request),
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	    (((nr - 0x40) < DRM_ETNAVIV_CALL_NR_MAX) && ((nr - 0x40) >= 0))
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	        ? (drm_call_to_string[nr - 0x40])
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	        : "UNKNOWN");
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	switch (nr) {
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	case 0: /* DRM_IOCTL_VERSION */
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		version = data;
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		*version = (drm_version_t){
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		    .version_major = 1,
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		    .version_minor = 1,
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		    .name_len = VERSION_NAME_LEN,
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		    .name = strdup(VERSION_NAME),
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		    .date_len = VERSION_DATE_LEN,
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		    .date = strdup(VERSION_DATE),
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		    .desc_len = VERSION_DESC_LEN,
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		    .desc = strdup(VERSION_DESC),
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		};
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		break;
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	case DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM:
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		res = etnaviv_gpu_get_param(&etnaviv_gpus[pipe], args->param,
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		    &args->value);
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		break;
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	case DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW:
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		res = etnaviv_ioctl_gem_new(dev, data, file);
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		break;
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	case DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO:
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		res = etnaviv_ioctl_gem_info(dev, data, file);
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		break;
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	case DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT:
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		res = etnaviv_ioctl_gem_submit(dev, data, file);
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		break;
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	case DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE:
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		res = etnaviv_ioctl_wait_fence(dev, data, file);
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		break;
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	default:
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		log_error("NIY, request=%x", nr);
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	}
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	return res;
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}
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#if 0
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static int etnaviv_dev_idesc_fstat(struct char_dev *cdev, void *buff) {
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	struct stat *st = buff;
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	st->st_rdev = makedev(226 /* Linux maj */, 0);
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	st->st_mode = S_IFCHR;
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	return 0;
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}
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#endif
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static int etnaviv_dev_idesc_status(struct char_dev *cdev, int mask) {
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	return 0;
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}
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#if 0
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static int ptr = 0;
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static void *etnaviv_dev_idesc_mmap(struct idesc *idesc, void *addr, size_t len,
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    int prot, int flags, int fd, off_t off) {
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	void *res = &etnaviv_uncached_buffer[ptr];
337
	struct drm_gem_object *obj;
338
	obj = (void *)(uint32_t)off;
339

340
	obj->dma_buf = res;
341

342
	ptr += len;
343

344
	memset(res, 0, len);
345

346
	return NULL;
347
}
348
#endif
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static void *etnaviv_dev_direct_access(struct char_dev *cdev, off_t off,
351
    size_t len) {
352
	if (off + len >= sizeof(etnaviv_uncached_buffer)) {
353
		return NULL;
354
	}
355

356
	return &etnaviv_uncached_buffer[off];
357
}
358

359
static struct char_dev_ops etnaviv_dev_ops = {
360
    .open = etnaviv_dev_open,
361
    .close = etnaviv_dev_close,
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    .ioctl = etnaviv_dev_idesc_ioctl,
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    .status = etnaviv_dev_idesc_status,
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    .direct_access = etnaviv_dev_direct_access,
365
};
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static struct char_dev etnaviv_dev = CHAR_DEV_INIT(etnaviv_dev, "card",
368
    &etnaviv_dev_ops);
369

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CHAR_DEV_REGISTER(&etnaviv_dev);
371

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PERIPH_MEMORY_DEFINE(vivante2d, VIVANTE_2D_BASE, 0x4000);
373
PERIPH_MEMORY_DEFINE(vivante3d, VIVANTE_3D_BASE, 0x4000);
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