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#include <drivers/common/memory.h>
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#include <embox/unit.h>
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#include <drivers/omap_gpmc.h>
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#include <drivers/gpmc.h>
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#define GPMC_MEMORY_START 0x00000000
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#define GPMC_MEMORY_END 0x3fffffff
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#define GPMC_CS_MEMORY_MAX 0x01000000
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#define GPMC_BASE_ADDRESS 0x6E000000
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EMBOX_UNIT_INIT(gpmc_init);
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uint32_t gpmc_reg_read(int offset) {
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return REG_LOAD(GPMC_BASE_ADDRESS + offset);
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void gpmc_reg_write(int offset, uint32_t val) {
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REG_STORE(GPMC_BASE_ADDRESS + offset, val);
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uint32_t gpmc_cs_reg_read(int cs, int offset) {
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unsigned long reg_addr;
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reg_addr = GPMC_BASE_ADDRESS + offset + (cs * GPMC_CS_SIZE);
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return REG_LOAD(reg_addr);
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void gpmc_cs_reg_write(int cs, int offset, uint32_t val) {
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unsigned long reg_addr;
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reg_addr = GPMC_BASE_ADDRESS + offset + (cs * GPMC_CS_SIZE);
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REG_STORE(reg_addr, val);
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int gpmc_cs_enabled(int cs) {
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l = gpmc_cs_reg_read(cs, GPMC_CS_CONFIG7);
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return l & GPMC_CONFIG7_CSVALID;
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static int gpmc_cs_enable_mem(int cs, uint32_t base, uint32_t size) {
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mask = (1 << GPMC_SECTION_SHIFT) - size;
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l = gpmc_cs_reg_read(cs, GPMC_CS_CONFIG7);
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l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
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l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
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l |= GPMC_CONFIG7_CSVALID;
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gpmc_cs_reg_write(cs, GPMC_CS_CONFIG7, l);
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vmem_map_region(vmem_current_context(), base, base, size, PROT_WRITE | PROT_READ | PROT_NOCACHE);
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int gpmc_cs_init(int cs, uint32_t *base, uint32_t size) {
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*base = GPMC_MEMORY_START + GPMC_CS_MEMORY_MAX * cs;
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return gpmc_cs_enable_mem(cs, *base, size);
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static int gpmc_init(void) {
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l = gpmc_reg_read(GPMC_REVISION);
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log_info("GPMC rev (major = %d minor = %d)", GPMC_REVISION_MAJOR(l), GPMC_REVISION_MINOR(l));
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PERIPH_MEMORY_DEFINE(omap_gpmc, GPMC_BASE_ADDRESS, 0x200);