embox

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/**
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 * @file socfpga.c
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 * @brief
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 * @author Denis Deryugin <deryugin.denis@gmail.com>
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 * @version
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 * @date 24.01.2020
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 */
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#include <errno.h>
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#include <string.h>
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#include <unistd.h>
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#include <drivers/common/memory.h>
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#include <drivers/fpga.h>
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#include <embox/unit.h>
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#include <framework/mod/options.h>
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#include <kernel/irq.h>
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#include <kernel/panic.h>
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#include <hal/reg.h>
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#include <util/log.h>
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#define SOCFPGA_L3_REGS             0xFF800000
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#define SOCFPGA_L3_REMAP            (SOCFPGA_L3_REGS + 0x00)
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#define SOCFPGA_SDRAM_REGS          0xFFC20000
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#define SOCFPGA_SDRAM_CONFIG        (SOCFPGA_SDRAM_REGS + 0x5080)
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#define SOCFPGA_RESETMGR_REGS       0xFFD05000
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#define SOCFPGA_RESETMGR_AXI_BRIDGE (SOCFPGA_RESETMGR_REGS + 0x1C)
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#define SOCFPGA_SYSMGR_REGS         0xFFD08000
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#define SOCFPGA_SYSMGR_INTF         (SOCFPGA_SYSMGR_REGS + 0x28)
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#define SOCFPGA_MGR_STAT            0x00
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# define SOCFPGA_MODE_MASK          0x7
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# define SOCFPGA_MODE_OFF           0x0
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# define SOCFPGA_MODE_RESET         0x1
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# define SOCFPGA_MODE_CONFIG        0x2
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# define SOCFPGA_MODE_INIT          0x3
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# define SOCFPGA_MODE_USER          0x4
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# define SOCFPGA_MODE_UNKNOWN       0x5
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#define SOCFPGA_MGR_CTRL            0x04
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# define SOCFPGA_CTRL_EN            (1 << 0)
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# define SOCFPGA_CTRL_NCE           (1 << 1)
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# define SOCFPGA_CTRL_NCONFIGPULL   (1 << 2)
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# define SOCFPGA_CTRL_CDRATIO_OFFT  6
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# define SOCFPGA_CTRL_AXICFEN       (1 << 8)
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# define SOCFPGA_CTRL_CFGWDTH       (1 << 9)
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#define SOCFPGA_MGR_DCLKCNT         0x08
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#define SOCFPGA_MGR_DCLKSTAT        0x0C
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# define SOCFPGA_DCLKSTAT_DONE      (1 << 0) /* W1C */
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#define SOCFPGA_MGR_GPO             0x10
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#define SOCFPGA_MGR_GPI             0x14
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#define SOCFPGA_MGR_MISCI           0x18
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#define SOCFPGA_MGR_GPIO_INTEN          0x830
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#define SOCFPGA_MGR_GPIO_INTMASK        0x834
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#define SOCFPGA_MGR_GPIO_INTTYPE_LEVEL  0x838
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#define SOCFPGA_MGR_GPIO_INT_POLARITY   0x83c
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#define SOCFPGA_MGR_GPIO_INTSTATUS      0x840
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#define SOCFPGA_MGR_GPIO_RAW_INTSTATUS  0x848
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#define SOCFPGA_MGR_GPIO_PORTA_EOI      0x84c
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#define SOCFPGA_MGR_GPIO_EXT_PORTA      0x850
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# define SOCFPGA_GPIO_EXT_PORTA_NSP     (1 << 9)
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# define SOCFPGA_GPIO_EXT_PORTA_CDP     (1 << 10)
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#define SOCFPGA_MGR_GPIO_LS_SYNC        0x860
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#define SOCFPGA_MGR_GPIO_VER_ID_CODE    0x86C
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#define SOCFPGA_MGR_GPIO_CONFIG_REG2    0x870
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#define SOCFPGA_MGR_GPIO_CONFIG_REG1    0x874
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#define TIMEOUT 10000
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/**
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 * @brief Reproduce `bridge_enable_handoff` command from u-boot
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 */
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static void bridge_enable_handoff(void) {
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#if 0
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	/* This code reprocudes "bridge_enable_handoff" from u-boot */
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	/* Pointer to some u-boot function. TODO: disassemble to figure out
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	 * what is being done here */
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	static const int (*fpga2sdram_apply)(void) = (void *) 0x3ff7d52c;
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	REG32_STORE(SOCFPGA_SYSMGR_INTF, 0);
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	fpga2sdram_apply();
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	REG32_STORE(SOCFPGA_SDRAM_CONFIG, 0);
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	REG32_STORE(SOCFPGA_RESETMGR_AXI_BRIDGE, 0);
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	REG32_STORE(SOCFPGA_L3_REMAP, 0x19);
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#endif
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}
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struct socfpga {
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	uintptr_t mgr_base;
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	uintptr_t mgr_data_addr;
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};
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static void socfpga_or(struct socfpga *socfpga, int offt, uint32_t val) {
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	uint32_t tmp = REG32_LOAD(socfpga->mgr_base + offt);
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	REG32_STORE(socfpga->mgr_base + offt, val | tmp);
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}
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static void socfpga_clear(struct socfpga *socfpga, int offt, uint32_t val) {
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	uint32_t tmp = REG32_LOAD(socfpga->mgr_base + offt);
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	REG32_STORE(socfpga->mgr_base + offt, tmp & ~val);
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}
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static uint32_t socfpga_read(struct socfpga *socfpga, int offt) {
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	return REG32_LOAD(socfpga->mgr_base + offt);
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}
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static void socfpga_write(struct socfpga *socfpga, int offt, uint32_t val) {
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	REG32_STORE(socfpga->mgr_base + offt, val);
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}
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static void socfpga_data_write(struct socfpga *socfpga, uint32_t val) {
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	REG32_STORE(socfpga->mgr_data_addr, val);
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}
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static void socfpga_regdump(struct socfpga *socfpga) {
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	log_debug(" STAT             %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_STAT));
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	log_debug(" CTRL             %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_CTRL));
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	log_debug(" DCLKCNT          %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_DCLKCNT));
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	log_debug(" DCLKSTAT         %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_DCLKSTAT));
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	log_debug(" GPO              %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPO));
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	log_debug(" GPI              %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPI));
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	log_debug(" MISCI            %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_MISCI));
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	log_debug(" GPIO_INTEN       %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_INTEN));
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	log_debug(" GPIO_INTMASK     %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_INTMASK));
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	log_debug(" GPIO_INTTYPE_LEV %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_INTTYPE_LEVEL));
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	log_debug(" GPIO_INT_POLARIT %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_INT_POLARITY));
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	log_debug(" GPIO_INTSTATUS   %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_INTSTATUS));
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	log_debug(" GPIO_RAW_INTSTAT %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_RAW_INTSTATUS));
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	log_debug(" GPIO_PORTA_EOI   %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_PORTA_EOI));
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	log_debug(" GPIO_EXT_PORTA   %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_EXT_PORTA));
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	log_debug(" GPIO_LS_SYNC     %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_LS_SYNC));
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	log_debug(" GPIO_VER_ID_CODE %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_VER_ID_CODE));
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	log_debug(" GPIO_CONFIG_REG2 %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_CONFIG_REG2));
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	log_debug(" GPIO_CONFIG_REG1 %08x",
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			socfpga_read(socfpga, SOCFPGA_MGR_GPIO_CONFIG_REG1));
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}
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static uint32_t socfpga_mode(struct socfpga *socfpga) {
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	uint32_t ret =
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		socfpga_read(socfpga, SOCFPGA_MGR_STAT) & SOCFPGA_MODE_MASK;
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	switch (ret) {
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	case SOCFPGA_MODE_MASK:
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	case SOCFPGA_MODE_OFF:
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	case SOCFPGA_MODE_RESET:
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	case SOCFPGA_MODE_CONFIG:
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	case SOCFPGA_MODE_INIT:
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	case SOCFPGA_MODE_USER:
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	case SOCFPGA_MODE_UNKNOWN:
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		return ret;
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	default:
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		log_error("incorrect socfpga state: 0x%x", ret);
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		return 0;
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	}
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}
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static int socfpga_mode_wait(struct socfpga *socfpga, uint32_t mode) {
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	int t = TIMEOUT;
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	while (t--) {
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		if (socfpga_mode(socfpga) == mode) {
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			break;
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		}
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		usleep(100);
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	}
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	if (t <= 0) {
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		log_error("FPGA reset timeout!");
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		return -ETIMEDOUT;
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	}
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	return 0;
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}
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static int socfpga_reset(struct socfpga *socfpga) {
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	/* Enable FPGA.
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	 * Note: this step is not mentioned in datasheet,
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	 * but is done in Linux driver */
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	socfpga_or(socfpga, SOCFPGA_MGR_CTRL,
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			SOCFPGA_CTRL_EN);
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	/* Enter reset state */
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	socfpga_or(socfpga, SOCFPGA_MGR_CTRL,
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			SOCFPGA_CTRL_NCONFIGPULL);
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	if (socfpga_mode_wait(socfpga, SOCFPGA_MODE_RESET)) {
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		return -ETIMEDOUT;
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	}
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	/* Exit reset phase */
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	socfpga_clear(socfpga, SOCFPGA_MGR_CTRL,
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			SOCFPGA_CTRL_NCONFIGPULL);
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	return 0;
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}
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/**
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 * @brief Corresponds to Power Up Phase, Reset Phase in docs
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 */
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static int socfpga_config_init(struct fpga *fpga) {
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	struct socfpga *socfpga = fpga->priv;
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	uint32_t tmp;
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	int err;
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	/* TODO: figure out what values should be actualy passed.
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	 * According to manual, "You must set the cdratio and
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	 * cfgwdth bits appropriatly" */
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	tmp = socfpga_read(socfpga, SOCFPGA_MGR_CTRL);
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	tmp &= ~SOCFPGA_CTRL_CDRATIO_OFFT;
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	tmp &= ~SOCFPGA_CTRL_CFGWDTH;
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	/* TODO: Set correct values */
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	socfpga_write(socfpga, SOCFPGA_MGR_CTRL, tmp);
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	err = socfpga_reset(socfpga);
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	if (err != 0) {
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		return err;
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	}
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	err = socfpga_mode_wait(socfpga, SOCFPGA_MODE_CONFIG);
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	if (err != 0) {
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		return -ETIMEDOUT;
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	}
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	/* Enable data transfer to FPGA */
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	socfpga_or(socfpga, SOCFPGA_MGR_CTRL, SOCFPGA_CTRL_AXICFEN);
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	return 0;
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}
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/**
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 * @brief Corresponds to Configuration Phase in docs
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 */
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static int socfpga_config_write(struct fpga *fpga, const uint8_t *buf, size_t len) {
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	struct socfpga *socfpga = fpga->priv;
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	uint32_t *buf32 = (uint32_t *) buf;
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	uint32_t tmp;
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	while (len > sizeof(uint32_t)) {
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		socfpga_data_write(socfpga, *buf32);
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		buf32++;
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		len -= 4;
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	}
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	if (len) {
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		tmp = 0;
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		memcpy(buf32, &tmp, len);
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		socfpga_data_write(socfpga, tmp);
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	}
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	return 0;
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}
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/**
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 * @brief Corresponds to Initialization Phase and User Mode in docs
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 */
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static int socfpga_config_complete(struct fpga *fpga) {
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	struct socfpga *socfpga = fpga->priv;
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	int err;
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	int timeout = TIMEOUT;
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	uint32_t tmp;
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	/* Wait for config write done */
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	while (timeout-- >= 0) {
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		tmp = socfpga_read(socfpga, SOCFPGA_MGR_GPIO_EXT_PORTA);
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		if ((tmp & SOCFPGA_GPIO_EXT_PORTA_NSP) &&
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			(tmp & SOCFPGA_GPIO_EXT_PORTA_CDP)) {
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			break;
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		}
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		usleep(100);
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	}
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	if (timeout <= 0) {
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		log_error("Timeout waiting for config write finish!");
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		return -ETIMEDOUT;
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	}
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	/* Disable data transfer */
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	socfpga_clear(socfpga, SOCFPGA_MGR_CTRL, SOCFPGA_CTRL_AXICFEN);
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	/* Send 4 clocks to FPGA.
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	 * Note: This is not mentioned in docs, but for some reason
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	 * HPS LED control example fails without this */
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	socfpga_write(socfpga, SOCFPGA_MGR_DCLKSTAT,
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			SOCFPGA_DCLKSTAT_DONE); /* W1C */
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	socfpga_write(socfpga, SOCFPGA_MGR_DCLKCNT, 4);
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	timeout = TIMEOUT;
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	while (timeout-- >= 0) {
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		tmp = socfpga_read(socfpga, SOCFPGA_MGR_DCLKSTAT);
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		if (tmp & SOCFPGA_DCLKSTAT_DONE) {
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			break;
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		}
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		usleep(100);
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	}
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	if (timeout <= 0) {
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		log_error("Timeout waiting for dclk!");
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		return -ETIMEDOUT;
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	}
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	err = socfpga_mode_wait(socfpga, SOCFPGA_MODE_USER);
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	if (err != 0) {
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		log_error("Timeout switching to User Mode!");
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		return err;
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	}
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	/* Disconnect FPGA manager. Note: this is not required by
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	 * the manual, but is done in Linux driver */
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	socfpga_clear(socfpga, SOCFPGA_MGR_CTRL, SOCFPGA_CTRL_EN);
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	return 0;
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}
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static struct fpga_ops socfpga_fpga_ops = {
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	.config_init     = socfpga_config_init,
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	.config_write    = socfpga_config_write,
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	.config_complete = socfpga_config_complete,
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};
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#define FPGA_MGR_BASE OPTION_GET(NUMBER, mgr_base_addr)
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#define FPGA_MGR_DATA OPTION_GET(NUMBER, mgr_data_addr)
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static struct socfpga socfpga0 = {
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	.mgr_base      = FPGA_MGR_BASE,
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	.mgr_data_addr = FPGA_MGR_DATA,
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};
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PERIPH_MEMORY_DEFINE(socfpga_mgr,      FPGA_MGR_BASE, 0x878);
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PERIPH_MEMORY_DEFINE(socfpga_mgr_data, FPGA_MGR_DATA, 0x4);
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/* TODO: this mapping should be moved to corresponding modules, but
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 * for now there are no modules for L3, SDRAM and System Manager, so
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 * these mappings are places where are they needed */
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PERIPH_MEMORY_DEFINE(socfpga_l3,       SOCFPGA_L3_REGS,       0x1000);
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PERIPH_MEMORY_DEFINE(socfpga_sdram,    SOCFPGA_SDRAM_REGS,    0x6000);
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PERIPH_MEMORY_DEFINE(socfpga_resetmgr, SOCFPGA_RESETMGR_REGS, 0x1000);
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PERIPH_MEMORY_DEFINE(socfpga_sysmgr,   SOCFPGA_SYSMGR_REGS,   0x1000);
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static irq_return_t socfpga_irq_handler(unsigned int irq_nr, void *data) {
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	log_debug("enter irq");
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	return IRQ_HANDLED;
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}
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EMBOX_UNIT_INIT(socfpga_init);
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static int socfpga_init(void) {
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	bridge_enable_handoff();
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	fpga_register(&socfpga_fpga_ops, &socfpga0);
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	socfpga_regdump(&socfpga0);
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	return irq_attach(OPTION_GET(NUMBER, irq_num),
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	                  socfpga_irq_handler,
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	                  0,
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	                  NULL,
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	                  "socfpga IRQ handler");
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}
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