embox

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/**
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 * @file sp804_timer.c
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 * @brief ARM Dual-Timer (SP804) Module driver
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 * @author Nishant Malpani <nish.malpani25@gmail.com>
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 * @date 2020-03-07
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 *
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 * @author Svirin Evgeny <eugenysvirin@gmail.com>
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 * @date 2021-02-20
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 */
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#include <drivers/common/memory.h>
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#include <hal/clock.h>
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#include <hal/reg.h>
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#include <kernel/irq.h>
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#include <kernel/printk.h>
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#include <kernel/time/clock_source.h>
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#include <kernel/time/time_device.h>
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#include <framework/mod/options.h>
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#include <embox/unit.h>
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#define SP804_BASE      OPTION_GET(NUMBER, base_addr) /* Base address */
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#define SP804_IRQ       OPTION_GET(NUMBER, irq_nr) /* Interrupt Request number */
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#define SP804_TARGET_HZ OPTION_GET(NUMBER, target_freq) /* Frequency to run the timer at */
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#define SP804_TIMCLK    OPTION_GET(NUMBER, TIMCLK_freq) /* Frequency of the SP804 clock timer - 1 mHz, frequency of subtraction from Timer1 Load Register */
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#define SP804_T1_LR     (SP804_BASE + 0x00) /* Timer1 Load Register */
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#define SP804_T1_VR     (SP804_BASE + 0x04) /* Timer1 Current Value Register */
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#define SP804_T1_CR     (SP804_BASE + 0x08) /* Timer1 Control Register */
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#define SP804_T1_ICR    (SP804_BASE + 0x0C) /* Timer1 Interrupt Clear Register */
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#define SP804_T1_RIS    (SP804_BASE + 0x10) /* Timer1 Raw Interrupt Status Register */
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#define SP804_T1_MIS    (SP804_BASE + 0x14) /* Timer1 Masked Interrupt Status Register */
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#define SP804_T1_BGL    (SP804_BASE + 0x18) /* Timer1 Background Load Register */
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#define SP804_CR_MASK       (0b11101111) /* Mask for bits 0-7 */
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#define SP804_CR_WRAPPING   (0 << 0) /* OneShot bit */
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#define SP804_CR_32BIT      (1 << 1) /* TimerSize bit */
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#define SP804_CR_TIMERPRE   (0 << 2) /* Prescale bits */
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#define SP804_CR_INTEN      (1 << 5) /* InterruptEnable bit */
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#define SP804_CR_PERIODIC   (1 << 6) /* TimerMode bit */
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#define SP804_CR_TIMEREN    (1 << 7) /* TimerEnable bit */
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#define SP804_ICR_CLEAR     (1 << 0) /* InterruptClear bit */
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#define SP804_PRESCALE          1 /* Prescaler operation - divide the rate of master clock */
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#define SP804_LR_VAL            ((SP804_TIMCLK) / (SP804_PRESCALE * SP804_TARGET_HZ))
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static irq_return_t clock_handler(unsigned int irq_nr, void *data) {
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    clock_tick_handler(data);
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    REG32_STORE(SP804_T1_ICR, SP804_ICR_CLEAR); /* Clear interrupts */
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    REG32_STORE(SP804_T1_LR, SP804_LR_VAL);
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    return IRQ_HANDLED;
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}
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static int sp804_timer_init(struct clock_source *cs) {
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    return irq_attach(SP804_IRQ,
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                      clock_handler,
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                      0,
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                      cs,
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                      "SP804");
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}
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static int this_set_periodic(struct clock_source *cs) {
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    /* Unset bits 0-7, also disables the timer to proceed with new config settings */
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    REG32_CLEAR(SP804_T1_CR, SP804_CR_MASK);
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    REG32_STORE(SP804_T1_LR, SP804_LR_VAL); /* Don't care in free-running mode */
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    /* setup Timer 1 as 32-bit interruptable periodic clocksource */
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    REG32_STORE(SP804_T1_CR, SP804_CR_32BIT | SP804_CR_INTEN | 
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                SP804_CR_PERIODIC | SP804_CR_TIMEREN);
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    return 0;
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}
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static cycle_t this_read(struct clock_source *cs) {
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    return REG32_LOAD(SP804_T1_VR);
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}
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static struct time_event_device sp804_timer_event = {
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    .set_periodic   = this_set_periodic,
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    .irq_nr   = SP804_IRQ,
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};
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static struct time_counter_device sp804_timer_counter = {
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    .read     = this_read,
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    .cycle_hz = 1000,
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};
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STATIC_IRQ_ATTACH(SP804_IRQ, clock_handler, &this_clock_source);
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PERIPH_MEMORY_DEFINE(sp804, SP804_BASE, 0x1C);
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CLOCK_SOURCE_DEF(sp804_timer, sp804_timer_init, NULL,
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	&sp804_timer_event, &sp804_timer_counter);
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