embox

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/**
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 * @file
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 * @brief Core clocking device in Raspberry PI
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 *
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 * See BCM2835-ARM-Peripherals.pdf, 12 chapter for details.
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 *
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 * A frequency of the System Timer is 1 MHz.
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 *
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 * @date 02.07.15
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 * @author Vita Loginova
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 */
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#include <drivers/common/memory.h>
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#include <hal/clock.h>
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#include <hal/reg.h>
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#include <hal/system.h>
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#include <kernel/irq.h>
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#include <kernel/time/clock_source.h>
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#include <sys/mman.h>
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#include <hal/mmu.h>
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#include <util/binalign.h>
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#include <framework/mod/options.h>
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#include <embox/unit.h>
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#define BCM2835_SYSTEM_TIMER_BASE OPTION_GET(NUMBER,base_addr)
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/**
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 * Layout of the System Timer Registers.
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 */
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struct raspi_timer_regs {
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	uint32_t CS;  /**< Control/Status */
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	uint32_t CLO; /**< Counter Lower 32 bits */
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	uint32_t CHI; /**< Counter Higher 32 bits */
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	uint32_t C0;  /**< Compare 0. DO NOT USE; is used by GPU.  */
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	uint32_t C1;  /**< Compare 1 */
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	uint32_t C2;  /**< Compare 2. DO NOT USE; is used by GPU.  */
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	uint32_t C3;  /**< Compare 3 */
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};
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/**
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 * Need to write one of these values into CS register to clear the
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 * match detect status bit and the corresponding interrupt request line.
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 */
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#define BCM2835_SYSTEM_TIMER_MATCH_0 (1 << 0)
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#define BCM2835_SYSTEM_TIMER_MATCH_1 (1 << 1)
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#define BCM2835_SYSTEM_TIMER_MATCH_2 (1 << 2)
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#define BCM2835_SYSTEM_TIMER_MATCH_3 (1 << 3)
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#define SYSTICK_IRQ 3
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#define CLOCK_DIVIDER 70
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#define RELOAD_VALUE (SYS_CLOCK / (CLOCK_DIVIDER * 1000))
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static volatile struct raspi_timer_regs * const regs =
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		(volatile struct raspi_timer_regs*)BCM2835_SYSTEM_TIMER_BASE;
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static inline void raspi_systick_clear(void) {
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	regs->CS = BCM2835_SYSTEM_TIMER_MATCH_3;
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}
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static inline void raspi_systick_comare(uint32_t value) {
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	regs->C3 = regs->CLO + value;
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}
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static irq_return_t clock_handler(unsigned int irq_nr, void *data) {
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	raspi_systick_clear();
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	raspi_systick_comare(RELOAD_VALUE);
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	clock_tick_handler(data);
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	return IRQ_HANDLED;
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}
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static int raspi_systick_init(struct clock_source *cs) {
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	irq_attach(SYSTICK_IRQ, clock_handler, 0, cs, "Raspberry PI systick timer");
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	return 0;
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}
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static int this_set_periodic(struct clock_source *cs) {
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	raspi_systick_clear();
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	/* From that point interrupts will occur. */
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	raspi_systick_comare(RELOAD_VALUE);
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	return 0;
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}
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static cycle_t this_read(struct clock_source *cs) {
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	return regs->CLO;
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}
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static struct time_event_device raspi_systick_event = {
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	.set_periodic = this_set_periodic,
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	.irq_nr = SYSTICK_IRQ,
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};
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static struct time_counter_device raspi_systick_counter = {
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	.read = this_read,
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	.cycle_hz = SYS_CLOCK / CLOCK_DIVIDER,
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};
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PERIPH_MEMORY_DEFINE(raspi_systick, BCM2835_SYSTEM_TIMER_BASE, sizeof(struct raspi_timer_regs));
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CLOCK_SOURCE_DEF(raspi_systick, raspi_systick_init, NULL,
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	&raspi_systick_event, &raspi_systick_counter);
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