embox

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/**
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 * @file
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 * @brief OMAP35x clock device driver
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 *
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 * @date 15.10.12
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 * @author Ilia Vaprol
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 */
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#include <drivers/common/memory.h>
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#include <drivers/irqctrl.h>
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#include <hal/clock.h>
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#include <hal/mmu.h>
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#include <hal/reg.h>
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#include <hal/system.h>
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#include <kernel/irq.h>
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#include <kernel/time/clock_source.h>
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#include <kernel/printk.h>
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#include <util/binalign.h>
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#include <embox/unit.h>
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/* omap's gptimer */
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#define CM_FCLKEN_WKUP  0x48004C00
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#define CM_ICLKEN_WKUP  0x48004C10
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#define CM_CLKSEL_WKUP  0x48004C40
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#define GPTIMER1_BASE ((void *) 0x48318000)
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#define GPTIMER1_IRQ 37
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struct gptimerxx_x {
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	uint32_t tidr; 		/* 0x00 */
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	char unused0[12];	/* 0x04 */
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	uint32_t cfg;		/* 0x10 */
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	uint32_t tistat;	/* 0x14 */
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	uint32_t tisr;		/* 0x18 */
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	uint32_t tier;		/* 0x1c */
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	uint32_t twer;		/* 0x20 */
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	uint32_t tclr;		/* 0x24 */
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	uint32_t tcrr;		/* 0x28 */
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	uint32_t tldr;		/* 0x2c */
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	uint32_t ttgr;		/* 0x30 */
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	uint32_t twps;		/* 0x34 */
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	uint32_t tmar;		/* 0x38 */
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	uint32_t tcar1;		/* 0x3c */
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	uint32_t tsicr;		/* 0x40 */
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	uint32_t tcar2;		/* 0x44 */
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	uint32_t tpir;		/* 0x48 */
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	uint32_t tnir;		/* 0x4c */
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	uint32_t tcvr;		/* 0x50 */
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	uint32_t tocr;		/* 0x54 */
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	uint32_t towr;		/* 0x54 */
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} __attribute__((packed));
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#define OMAP_LOAD_VALUE 0xffffffe0
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/* common register values */
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#define GPTIMER_TCLR_START	(1 << 0)
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#define GPTIMER_TCLR_AUTORELOAD (1 << 1)
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#define GPTIMER_TIER_OVERFLOW   (1 << 1)
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#define GPTIMER_TISR_OVERFLOW   (1 << 1)
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static irq_return_t clock_handler(unsigned int irq_nr, void *data) {
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	volatile struct gptimerxx_x *gptimer = GPTIMER1_BASE;
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	clock_tick_handler(data);
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	REG_STORE(&gptimer->tisr, GPTIMER_TISR_OVERFLOW);
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	return IRQ_HANDLED;
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}
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static int omap3_clk_set_periodic(struct clock_source *cs) {
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	volatile struct gptimerxx_x *gptimer = GPTIMER1_BASE;
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	REG_ORIN(CM_FCLKEN_WKUP, 1);
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	REG_ORIN(CM_ICLKEN_WKUP, 1);
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	REG_ANDIN(CM_CLKSEL_WKUP, ~1);
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	REG_STORE(&gptimer->cfg, 0x2);
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	REG_STORE(&gptimer->tpir, 232000);
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	REG_STORE(&gptimer->tnir, -768000);
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	REG_STORE(&gptimer->tcrr, OMAP_LOAD_VALUE);
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	REG_STORE(&gptimer->tldr, OMAP_LOAD_VALUE);
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	REG_STORE(&gptimer->tclr, GPTIMER_TCLR_START | GPTIMER_TCLR_AUTORELOAD);
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	REG_STORE(&gptimer->tier, GPTIMER_TIER_OVERFLOW);
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	REG_STORE(&gptimer->twer, GPTIMER_TIER_OVERFLOW);
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	return 0;
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}
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static struct time_event_device omap3_clk_event = {
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	.set_periodic = omap3_clk_set_periodic,
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	.irq_nr = GPTIMER1_IRQ,
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};
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static int omap_clk_init(struct clock_source *cs) {
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	/* Map one vmem page to handle this device if mmu is used */
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	return irq_attach(GPTIMER1_IRQ, clock_handler, 0, cs, "omap3_clk");
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}
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PERIPH_MEMORY_DEFINE(omap3_gptimer, (uintptr_t) GPTIMER1_BASE, 0x1000);
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PERIPH_MEMORY_DEFINE(omap3_cm, CM_FCLKEN_WKUP, 0x50);
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CLOCK_SOURCE_DEF(omap3_clk, omap_clk_init, NULL,
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	&omap3_clk_event, NULL);
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