embox

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/**
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 * @file
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 *
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 * @brief Implementation for microblaze timers
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 *
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 * @date 19.11.09
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 * @author Anton Bondarev
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 */
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#include <drivers/common/memory.h>
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#include <asm/bitops.h>
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#include <hal/clock.h>
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#include <hal/system.h>
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#include <kernel/irq.h>
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#include <kernel/panic.h>
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#include <kernel/time/clock_source.h>
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#include <kernel/time/ktime.h>
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#include <embox/unit.h>
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#include <module/embox/driver/clock/mb_timer.h>
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#define CONFIG_XILINX_TIMER_BASEADDR OPTION_GET(NUMBER,mbtimer_base)
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#define CONFIG_XILINX_TIMER_IRQ      OPTION_GET(NUMBER,irq_num)
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#define TIMER_PRELOAD (SYS_CLOCK / 1000)
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/*bits definition of cntl/status (tcsr) register*/
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#define TIMER_ENALL_BIT  21      /**< ENALL */
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#define TIMER_PWM_BIT    22      /**< PWM */
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#define TIMER_INT_BIT    23      /**< TxINT */
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#define TIMER_ENT_BIT    24      /**< ENT */
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#define TIMER_ENIT_BIT   25      /**< ENIT */
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#define TIMER_LOAD_BIT   26      /**< LOAD */
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#define TIMER_ARHT_BIT   27      /**< ARHT */
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#define TIMER_CAPT_BIT   28      /**< CAPT */
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#define TIMER_GENT_BIT   29      /**< GENT */
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#define TIMER_UDT_BIT    30      /**< UDT */
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#define TIMER_MDT        31      /**< MDT */
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/** enable both timers t0 and t1.
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 * clearing this bit isn't change state ENT bit */
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#define TIMER_ENABLE_ALL    REVERSE_MASK(TIMER_ENALL_BIT)
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/** interrupt was pending. Write '1' for clearing this bit*/
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#define TIMER_INT           REVERSE_MASK(TIMER_INT_BIT)
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/** enable timer*/
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#define TIMER_ENABLE        REVERSE_MASK(TIMER_ENT_BIT)
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/** enable timer interrupt*/
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#define TIMER_INT_ENABLE    REVERSE_MASK(TIMER_ENIT_BIT)
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/** load value from tlr register*/
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#define TIMER_RESET         REVERSE_MASK(TIMER_LOAD_BIT)
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/** set reload mode*/
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#define TIMER_RELOAD        REVERSE_MASK(TIMER_ARHT_BIT)
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/** set down count mode*/
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#define TIMER_DOWN_COUNT    REVERSE_MASK(TIMER_UDT_BIT)
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static struct time_event_device mb_ed;
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/**
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 * Structure one of two timers. Both timers need only for pwm mode
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 */
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typedef volatile struct timer_regs {
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	uint32_t tcsr; /**< control/status register TCSR */
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	uint32_t tlr; /**< load register TLR */
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	uint32_t tcr; /**< timer/counter register */
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} timer_regs_t;
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/**
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 * Microblaze timer module contains two timer module, each of them is described
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 * in @link srtuct timer_regs @endlink
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 */
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typedef volatile struct mb_timers {
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	timer_regs_t tmr0;
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	timer_regs_t tmr1;
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} mb_timers_t;
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static mb_timers_t *timers = (mb_timers_t *) CONFIG_XILINX_TIMER_BASEADDR;
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#define timer0 (&timers->tmr0)
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/*
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 * we must use proxy for interrupt handler because we must clean bit in register
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 * timer.
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 */
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static irq_return_t clock_handler(unsigned int irq_nr, void *dev_id) {
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	clock_tick_handler(dev_id);
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	timer0->tcsr |= TIMER_INT;
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	return IRQ_HANDLED;
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}
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static cycle_t mb_cycle_read(struct clock_source *cs) {
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	return TIMER_PRELOAD - timer0->tcr;
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}
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static int mb_timer_init(struct clock_source *cs) {
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	if (0 != irq_attach(CONFIG_XILINX_TIMER_IRQ, clock_handler, 0, cs, "mbtimer")) {
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		panic("mbtimer irq_attach failed");
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	}
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	return 0;
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}
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static int mb_clock_setup(struct clock_source *cs) {
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	/*set clocks period*/
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	timer0->tlr = TIMER_PRELOAD;
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	/*clear interrupts bit and load value from tlr register*/
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	timer0->tcsr = TIMER_INT | TIMER_RESET;
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	/*start timer*/
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	timer0->tcsr = TIMER_ENABLE | TIMER_INT_ENABLE | TIMER_RELOAD
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			| TIMER_DOWN_COUNT;
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	return 0;
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}
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static struct time_event_device mb_ed = {
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	.set_periodic = mb_clock_setup,
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	.name = "mb_timer",
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	.irq_nr = CONFIG_XILINX_TIMER_IRQ
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};
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static struct time_counter_device mb_cd = {
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	.read = mb_cycle_read,
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	.cycle_hz = SYS_CLOCK,
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};
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PERIPH_MEMORY_DEFINE(mb_timer, CONFIG_XILINX_TIMER_BASEADDR, sizeof(struct timer_regs));
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CLOCK_SOURCE_DEF(mb_timer, mb_timer_init, NULL,
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	&mb_ed, &mb_cd);
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