embox

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/**
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 * @file imx6_gpt.c
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 * @brief General Purpose Timer for i.MX6 board
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 * @author Denis Deryugin <deryugin.denis@gmail.com>
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 * @version 0.1
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 * @date 2016-06-12
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 *
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 * @author Evgeny Svirin <eugenysvirin@gmail.com>
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 * @date 2021-04-9
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 */
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#include <sys/mman.h>
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#include <drivers/common/memory.h>
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#include <hal/clock.h>
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#include <hal/reg.h>
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#include <kernel/irq.h>
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#include <kernel/printk.h>
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#include <kernel/time/clock_source.h>
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#include <kernel/time/time_device.h>
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#include <framework/mod/options.h>
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#include <embox/unit.h>
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#define GPT_BASE      OPTION_GET(NUMBER, base_addr)
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#define GPT_IRQ       OPTION_GET(NUMBER, irq_nr)
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#define GPT_TARGET_HZ OPTION_GET(NUMBER, freq)
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#define GPT_PRESCALER 0 /* 2^0 */
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#define GPT_CR   (GPT_BASE + 0x00) /* Control register */
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#define GPT_PR   (GPT_BASE + 0x04) /* Prescaler register */
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#define GPT_SR   (GPT_BASE + 0x08) /* Status register */
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#define GPT_IR   (GPT_BASE + 0x0C) /* Interrupt register */
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#define GPT_OCR1 (GPT_BASE + 0x10) /* Output compare register 1 */
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#define GPT_OCR2 (GPT_BASE + 0x14) /* Output compare register 2 */
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#define GPT_OCR3 (GPT_BASE + 0x18) /* Output compare register 3 */
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#define GPT_ICR1 (GPT_BASE + 0x1C) /* Input capture register 1 */
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#define GPT_ICR2 (GPT_BASE + 0x20) /* Input capture register 2 */
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#define GPT_CNT  (GPT_BASE + 0x24) /* Counter register */
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#define GPT_IR_INT1   (1 << 0)     /* Enable interruption on OutputCompare1 */
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#define GPT_CR_MASK   (0b10000011) /* Enable interruptable periodic timer mode */
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#define GPT_SR_CLR    (0)          /* Clear status mask */
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#define GPT_CR_EN     (1u <<  0)
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#define GPT_CR_ENMOD  (1u <<  1)
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#define GPT_CR_DBGEN  (1u <<  2)
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#define GPT_CR_WAITEN (1u <<  3)
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#define GPT_CR_DOZEEN (1u <<  4)
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#define GPT_CR_STOPEN (1u <<  5)
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#define GPT_CR_FRR    (1u <<  9)
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#define GPT_CR_SWR    (1u << 15)
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#define GPT_CR_FO1    (1u << 29)
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#define GPT_CR_FO2    (1u << 30)
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#define GPT_CR_FO3    (1u << 31)
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#define GPT_CR_CLKSRC_OFFT  6
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#define GPT_CR_IM1_OFFT    16
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#define GPT_CR_IM2_OFFT    18
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#define GPT_CR_OM1_OFFT    20
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#define GPT_CR_OM2_OFFT    23
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#define GPT_CR_OM3_OFFT    26
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#define GPT_IR_OF1IE (1 << 0)
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#define CLKSRC_PERIPH  1
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#define CLKSRC_LOWFREQ 4
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/* By default, periphal clock source is PPL2, 528MHz */
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#define _BASE_HZ     528000000
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#define _BASE_SCALER 8
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static irq_return_t clock_handler(unsigned int irq_nr, void *data) {
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	clock_tick_handler(data);
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	REG32_CLEAR(GPT_SR, GPT_SR_CLR);
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	return IRQ_HANDLED;
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}
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static int imx6_gpt_init(struct clock_source *cs) {
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	/* We can configure GPT only when disabled */
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	REG32_STORE(GPT_CR,   0);
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	REG32_STORE(GPT_IR,   0);
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	return irq_attach(GPT_IRQ,
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	                  clock_handler,
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	                  0,
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	                  cs,
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	                  "i.MX6 General Purpose Timer");
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}
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static int imx6_gpt_set_periodic(struct clock_source *cs) {
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	REG32_STORE(GPT_PR, GPT_PRESCALER);
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	REG32_STORE(GPT_OCR1, _BASE_HZ / _BASE_SCALER / GPT_TARGET_HZ); 
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	REG32_STORE(GPT_IR, GPT_IR_INT1);
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	REG32_STORE(GPT_CR, GPT_CR_MASK); 
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	return 0;
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}
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static cycle_t imx6_gpt_read(struct clock_source *cs) {
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	return REG32_LOAD(GPT_CNT);
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}
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static struct time_event_device imx6_gpt_event = {
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	.set_periodic   = imx6_gpt_set_periodic,
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	.irq_nr   = GPT_IRQ,
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};
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static struct time_counter_device imx6_gpt_counter = {
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	.read     = imx6_gpt_read,
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	.cycle_hz = GPT_TARGET_HZ,
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};
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STATIC_IRQ_ATTACH(GPT_IRQ, clock_handler, &this_clock_source);
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PERIPH_MEMORY_DEFINE(imx_gpt, GPT_BASE, 0x40);
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CLOCK_SOURCE_DEF(imx6_gpt,  imx6_gpt_init, NULL,
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	&imx6_gpt_event, &imx6_gpt_counter);
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