embox

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/**
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 * @file
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 * @brief Gaisler Research GPTIMER General Purpose Timer Unit driver.
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 *
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 * @date 19.11.09
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 * @author Anton Bondarev
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 * @author Eldar Abusalimov
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 */
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#include <assert.h>
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#include <stdint.h>
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#include <errno.h>
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#include <drivers/amba_pnp.h>
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#include <hal/clock.h>
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#include <hal/reg.h>
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#include <hal/system.h>
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#include <kernel/irq.h>
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#include <kernel/panic.h>
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#include <kernel/time/clock_source.h>
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#include <kernel/time/ktime.h>
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#include <embox/unit.h>
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#define SCALER_RELOAD (SYS_CLOCK / 1000000 - 1)
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#define TIMER0_RELOAD (1000000 / 1000 - 1)
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#define CTRL_EN (1 << 0) /**< Enable. */
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#define CTRL_RS (1 << 1) /**< Restart. */
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#define CTRL_LD (1 << 2) /**< Load. */
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#define CTRL_IE (1 << 3) /**< Interrupt Enable. */
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#define CTRL_IP (1 << 4) /**< Interrupt Pending. */
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#define CTRL_CH (1 << 5) /**< Chain. */
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#define CTRL_DH (1 << 6) /**< Debug Halt. */
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#define CTRL_INITIAL (CTRL_EN | CTRL_RS | CTRL_LD | CTRL_IE)
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#define CFG_NTIMERS(cfg_reg) (cfg_reg & 0x7)
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#define CFG_IRQ(cfg_reg)    ((cfg_reg >> 3) & 0x1f)
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#define CFG_SI(cfg_reg)     ((cfg_reg >> 8) & 0x1) /**< Separate interrupts. */
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/**
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 * General Purpose Timer Unit registers.
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 */
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struct gptimer_regs {
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	/**
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	 * The prescaler is clocked by the system clock and decremented on each
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	 * clock cycle.
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	 */
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	/* 0x00 */uint32_t scaler_counter;
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	/**
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	 * When the prescaler underflows,
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	 * it is reloaded from the prescaler reload
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	 * register and a timer tick is generated.
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	 */
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	/* 0x04 */uint32_t scaler_reload;
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	/*-------+----+----+-----+---------+
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	 | resrv | DF | SI | IRQ | ntimers |
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	 | 31-10 | 9  | 8  | 7-3 | 2-0     |
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	 +-------+----+----+-----+---------*/
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	/* 0x08 */uint32_t cfg;
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	/* Just a place holder. */
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	/* 0x0C */uint32_t dummy;
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	/**
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	 * Register sets for each implemented timer.
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	 */
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	struct timer_entry {
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		/**
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		 * Timer Counter value.
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		 * Decremented by 1 for each prescaler tick.
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		 */
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		/* 0xn0 */uint32_t counter;
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		/**
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		 * Timer Reload value.
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		 * This value is loaded into the timer counter
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		 * value register when the LD bit is written to
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		 * load bit in the timers control register or when
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		 * the RS bit is set in the control register and the
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		 * timer underflows.
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		 */
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		/* 0xn4 */uint32_t reload;
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		/*------+----+----+----+----+----+----+----+
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		 | resv | DH | CH | IP | IE | LD | RS | EN |
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		 | 31-7 | 6  | 5  | 4  | 3  | 2  | 1  | 0  |
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		 +------+----+----+----+----+----+----+----*/
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		/* 0xn8 */uint32_t ctrl;
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		/* Just a place holder. */
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		/* 0xnC */uint32_t dummy;
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	} timer[];
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};
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static volatile struct gptimer_regs *dev_regs;
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static int dev_regs_init(unsigned int *irq_nr);
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static struct time_event_device gptimer_ed;
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static irq_return_t clock_handler(unsigned int irq_nr, void *dev_id) {
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	// XXX clock_hander is called from arch part
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	clock_tick_handler(dev_id);
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	return IRQ_HANDLED;
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}
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static int gptimer_init(struct clock_source *cs) {
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	uint32_t cfg_reg;
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	unsigned int irq_nr;
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	int i;
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	if (NULL != dev_regs) {
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		return 0;
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	}
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	if (0 != dev_regs_init(&irq_nr)) {
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		panic("Unable to initialize gptimer dev_regs");
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	}
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	assert(NULL != dev_regs);
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	gptimer_ed.irq_nr = irq_nr;
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	cfg_reg = REG_LOAD(&dev_regs->cfg);
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	for (i = 0; i < CFG_NTIMERS(cfg_reg); ++i) {
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		REG_STORE(&dev_regs->timer[i].ctrl, 0x0);
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	}
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	REG_STORE(&dev_regs->scaler_reload, SCALER_RELOAD);
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	REG_STORE(&dev_regs->scaler_counter, 0);
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	return irq_attach(irq_nr, clock_handler, 0, cs, "gptimer");
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}
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static int gptimer_set_periodic(struct clock_source *cs);
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static cycle_t gptimer_read(struct clock_source *cs) {
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	return TIMER0_RELOAD - REG_LOAD(&dev_regs->timer[0].counter);
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}
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static struct time_event_device gptimer_ed = {
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	.set_periodic = gptimer_set_periodic ,
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};
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static struct time_counter_device gptimer_cd = {
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	.read = gptimer_read,
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	.cycle_hz = 1000000,
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};
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static int gptimer_set_periodic(struct clock_source *cs) {
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	REG_STORE(&dev_regs->timer[0].reload, TIMER0_RELOAD);
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	REG_STORE(&dev_regs->timer[0].counter, 0);
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	REG_STORE(&dev_regs->timer[0].ctrl, CTRL_INITIAL);
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	return 0;
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}
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#ifdef DRIVER_AMBAPP
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static int dev_regs_init(unsigned int *irq_nr) {
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	amba_dev_t amba_dev;
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	assert(NULL != irq_nr);
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	if (-1 == capture_amba_dev(&amba_dev, AMBAPP_VENDOR_GAISLER,
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			AMBAPP_DEVICE_GAISLER_GPTIMER, false, false)) {
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		printk("can't capture apb dev venID=0x%X, devID=0x%X\n",
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				AMBAPP_VENDOR_GAISLER, AMBAPP_DEVICE_GAISLER_GPTIMER);
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		return -ENODEV;
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	}
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	dev_regs = (struct gptimer_regs *) amba_dev.bar[0].start;
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	*irq_nr = amba_dev.dev_info.irq;
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	return 0;
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}
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#elif OPTION_DEFINED(NUMBER,gptimer_base)
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static int dev_regs_init(unsigned int *irq_nr) {
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	assert(NULL != irq_nr);
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	dev_regs = (volatile struct gptimer_regs *) OPTION_GET(NUMBER,gptimer_base);
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	*irq_nr = OPTION_GET(NUMBER,irq_num);
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	return 0;
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}
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#else
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# error "Either DRIVER_AMBAPP or gptimer_base must be defined"
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#endif /* DRIVER_AMBAPP */
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CLOCK_SOURCE_DEF(gptimer, gptimer_init, NULL,
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	&gptimer_ed, &gptimer_cd);
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