embox

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/**
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 * @file e2k.c
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 * @brief Stub
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 * @author Denis Deryugin <deryugin.denis@gmail.com>
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 * @version
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 * @date 20.12.2017
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 */
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#include <util/log.h>
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#include <stdint.h>
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#include <asm/io.h>
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#include <embox/unit.h>
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#include <framework/mod/options.h>
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#include <hal/clock.h>
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#include <kernel/irq.h>
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#include <kernel/time/clock_source.h>
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#include <kernel/time/time_device.h>
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#include <hal/ipl.h>
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#include <e2k_api.h>
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#include <e2k_mas.h>
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#include <asm/mpspec.h>
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static uint64_t clock_base = 0;
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#define E2K_CLOCK_BASE ((uint32_t)clock_base)
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#define IRQ_NR     OPTION_GET(NUMBER, irq_num)
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#define LT_FREQ    OPTION_GET(NUMBER, freq)
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#define E2K_COUNTER_LIMIT	(E2K_CLOCK_BASE + 0x00)
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#define E2K_COUNTER_START_VALUE	(E2K_CLOCK_BASE + 0x04)
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#define E2K_COUNTER		(E2K_CLOCK_BASE + 0x08)
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#define E2K_COUNTER_CONTROL	(E2K_CLOCK_BASE + 0x0c)
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#define E2K_WD_COUNTER		(E2K_CLOCK_BASE + 0x10)
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#define E2K_WD_COUNTER_LOW	(E2K_CLOCK_BASE + 0x10)
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#define E2K_WD_COUNTER_HIGH	(E2K_CLOCK_BASE + 0x14)
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#define E2K_WD_LIMIT		(E2K_CLOCK_BASE + 0x18)
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#define E2K_POWER_COUNTER	(E2K_CLOCK_BASE + 0x1c)
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#define E2K_POWER_COUNTER_LOW	(E2K_CLOCK_BASE + 0x1c)
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#define E2K_POWER_COUNTER_HIGH	(E2K_CLOCK_BASE + 0x20)
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#define E2K_WD_CONTROL		(E2K_CLOCK_BASE + 0x24)
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#define E2K_RESET_COUNTER	(E2K_CLOCK_BASE + 0x28)
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#define E2K_RESET_COUNTER_LOW	(E2K_CLOCK_BASE + 0x28)
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#define E2K_RESET_COUNTER_HIGH	(E2K_CLOCK_BASE + 0x2c)
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/* counters registers structure */
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#define	LT_COUNTER_SHIFT	9	/* [30: 9] counters value */
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#define	LT_COUNTER_LIMIT_SHIFT	31	/* [31] Limit bit */
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#define	LT_COUNTER_LIMIT_BIT	(1 << LT_COUNTER_LIMIT_SHIFT)
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#define	LT_WRITE_COUNTER_VALUE(count)	((count) << LT_COUNTER_SHIFT)
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#define	LT_READ_COUNTER_VALUE(count)	((count) >> LT_COUNTER_SHIFT)
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#define	LT_NSEC_PER_COUNTER_INCR	100	/* 10 MHz == 100 nunosec */
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/* counter control register structure */
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#define	LT_COUNTER_CNTR_START	0x00000001	/* start/stop timer */
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#define	LT_COUNTER_CNTR_INVERTL	0x00000002	/* invert limit bit */
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#define	LT_COUNTER_CNTR_LINIT	0x00000004	/* Limit bit initial state */
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						/* 1 - limit bit set to 1 */
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#define	LT_COUNTER_CNTR_LAUNCH	(LT_COUNTER_CNTR_START)
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#define	LT_INVERT_COUNTER_CNTR_LAUNCH	(LT_COUNTER_CNTR_LAUNCH | \
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						LT_COUNTER_CNTR_INVERTL | \
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						LT_COUNTER_CNTR_LINIT)
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#define	LT_COUNTER_CNTR_STOP	(0)
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#define WD_CLOCK_TICK_RATE 10000000L
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#define WD_LATCH(tick_rate) (((tick_rate) + HZ/2) / HZ)
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#define WD_LIMIT_SHIFT	12
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#define	WD_WRITE_COUNTER_VALUE(count) (count)
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#define	WD_READ_COUNTER_VALUE(count) ((count) << WD_LIMIT_SHIFT)
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#define WD_SET_COUNTER_VAL(sek)	\
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		(WD_WRITE_COUNTER_VALUE(WD_CLOCK_TICK_RATE * (sek)))
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#define	WD_INTR_MODE	0x1
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#define	WD_ENABLE	0x2
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#define	WD_EVENT	0x4
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static irq_return_t e2k_clock_handler(unsigned int irq_nr, void *dev_id) {
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	clock_tick_handler(dev_id);
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	return IRQ_HANDLED;
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}
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static int e2k_clock_init(struct clock_source *cs) {
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	uint32_t clock_hz = (10000000 + LT_FREQ / 2) / LT_FREQ;
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	clock_base = mpspec_get_clock_base();
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	if (clock_base == 0) {
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		log_error(" Error: MP_TIMER record not found, ");
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		return -1;
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	}
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	irq_attach(IRQ_NR, e2k_clock_handler, 0, cs, "e2k clock");
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	/* Setup frequency */
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	e2k_write32(clock_hz << 9, E2K_COUNTER_LIMIT);
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	e2k_write32(LT_INVERT_COUNTER_CNTR_LAUNCH, E2K_COUNTER_CONTROL);
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	return 0;
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}
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static int e2k_clock_set_periodic(struct clock_source *cs) {
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	return 0;
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}
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static cycle_t e2k_clock_read(struct clock_source *cs) {
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	cycle_t res;
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	res = e2k_read64(E2K_POWER_COUNTER);
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	return res;
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}
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static struct time_event_device e2k_clock_event = {
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	.set_periodic   = e2k_clock_set_periodic,
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	.irq_nr = IRQ_NR
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};
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static struct time_counter_device e2k_clock_counter = {
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	.read     = e2k_clock_read,
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	.cycle_hz = 10000000,
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};
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CLOCK_SOURCE_DEF(e2k_clock, e2k_clock_init, NULL,
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		&e2k_clock_event, &e2k_clock_counter);
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