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sun4i_timer.c
176 строк · 5.6 Кб
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/**
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 * @file
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 *
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 * @date Mar 17, 2023
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 * @author Anton Bondarev
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 */
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#include <util/log.h>
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#include <stdint.h>
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#include <sys/mman.h>
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#include <drivers/common/memory.h>
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#include <hal/clock.h>
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#include <hal/reg.h>
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#include <hal/system.h>
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#include <kernel/irq.h>
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#include <kernel/time/clock_source.h>
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#include <embox/unit.h>
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#include <framework/mod/options.h>
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#include <embox/unit.h>
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#define BASE_ADDR     OPTION_GET(NUMBER, base_addr)
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#define IRQ_NUM       OPTION_GET(NUMBER, irq_num)
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#define BIT(nr)                     (1UL << (nr))
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#define TIMER_IRQ_EN_REG          0x00
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#define TIMER_IRQ_EN(val)         BIT(val)
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#define TIMER_IRQ_ST_REG          0x04
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#define TIMER_CTL_REG(val)        (0x10 * val + 0x10)
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#define TIMER_CTL_ENABLE          BIT(0)
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#define TIMER_CTL_RELOAD          BIT(1)
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#define TIMER_CTL_CLK_SRC(val)    (((val) & 0x3) << 2)
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#define TIMER_CTL_CLK_SRC_OSC24M  (1)
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#define TIMER_CTL_CLK_PRES(val)   (((val) & 0x7) << 4)
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#define TIMER_CTL_ONESHOT         BIT(7)
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#define TIMER_INTVAL_REG(val)     (0x10 * (val) + 0x14)
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#define TIMER_CNTVAL_REG(val)     (0x10 * (val) + 0x18)
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#define TIMER_SYNC_TICKS          3
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static inline void allwinner_sun4i_clkevt_sync(void  *base) {
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	uint32_t old = REG32_LOAD(base + TIMER_CNTVAL_REG(1));
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	while ((old - REG32_LOAD(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS) {
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	//	cpu_relax();
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	}
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}
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static inline void allwinner_sun4i_clkevt_time_stop(void *base, uint8_t timer) {
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	uint32_t val = REG32_LOAD(base + TIMER_CTL_REG(timer));
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	REG32_STORE(base + TIMER_CTL_REG(timer), val & ~TIMER_CTL_ENABLE);
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	allwinner_sun4i_clkevt_sync(base);
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}
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static inline void allwinner_sun4i_clkevt_time_setup(void *base, uint8_t timer, uint32_t delay) {
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	REG32_STORE(base + TIMER_INTVAL_REG(timer), delay);
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}
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static inline void allwinner_sun4i_clkevt_time_start(void *base, uint8_t timer, int periodic) {
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	uint32_t val = REG32_LOAD(base + TIMER_CTL_REG(timer));
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	if (periodic) {
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		val &= ~TIMER_CTL_ONESHOT;
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	} else{
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		val |= TIMER_CTL_ONESHOT;
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	}
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	REG32_STORE((base + TIMER_CTL_REG(timer)), val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD);
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}
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static inline void allwinner_sun4i_timer_clear_interrupt(void *base) {
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	REG32_STORE(base + TIMER_IRQ_ST_REG, TIMER_IRQ_EN(0));
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}
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static inline void allwinner_sun4i_show_regs(void) {
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	log_debug("\n**********************");
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	log_debug("0x00 TIMER_IRQ_EN_REG: 0x%8x", REG32_LOAD(BASE_ADDR + TIMER_IRQ_EN_REG));
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	log_debug("0x04 TIMER_IRQ_ST_REG: 0x%8x", REG32_LOAD(BASE_ADDR + TIMER_IRQ_ST_REG));
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	log_debug("0x10 TIMER_CTL_REG(0): 0x%8x", REG32_LOAD(BASE_ADDR + TIMER_CTL_REG(0)));
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	log_debug("0x14 TIMER_INTVAL_REG(0): 0x%8x", REG32_LOAD(BASE_ADDR + TIMER_INTVAL_REG(0)));
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	log_debug("0x18 TIMER_CNTVAL_REG(0): 0x%8x", REG32_LOAD(BASE_ADDR + TIMER_CNTVAL_REG(0)));
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	log_debug("0x20 TIMER_CTL_REG(1): 0x%8x", REG32_LOAD(BASE_ADDR + TIMER_CTL_REG(1)));
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	log_debug("0x24 TIMER_INTVAL_REG(1): 0x%8x", REG32_LOAD(BASE_ADDR + TIMER_INTVAL_REG(1)));
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	log_debug("0x28 TIMER_CNTVAL_REG(1): 0x%8x", REG32_LOAD(BASE_ADDR + TIMER_CNTVAL_REG(1)));
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}
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static irq_return_t allwinner_sun4i_timer_handler(unsigned int irq_nr, void *dev_id) {
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	allwinner_sun4i_timer_clear_interrupt((void *)(uintptr_t)BASE_ADDR);
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	clock_tick_handler(dev_id);
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	return IRQ_HANDLED;
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}
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static int allwinner_sun4i_timer_set_oneshot(struct clock_source *cs) {
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	allwinner_sun4i_clkevt_time_stop((void *)(uintptr_t)BASE_ADDR, 0);
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	allwinner_sun4i_clkevt_time_start((void *)(uintptr_t)BASE_ADDR, 0, false);
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	allwinner_sun4i_show_regs();
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	return ENOERR;
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}
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static int allwinner_sun4i_timer_set_periodic(struct clock_source *cs) {
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	allwinner_sun4i_clkevt_time_stop((void *)(uintptr_t)BASE_ADDR, 0);
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	allwinner_sun4i_clkevt_time_setup((void *)(uintptr_t)BASE_ADDR, 0, 25000); //cs->event_device->event_hz);
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	allwinner_sun4i_clkevt_time_start((void *)(uintptr_t)BASE_ADDR, 0, true);
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	allwinner_sun4i_show_regs();
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	return ENOERR;
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}
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static int allwinner_sun4i_timer_set_next_event(struct clock_source *cs,
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		uint32_t next_event) {
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	allwinner_sun4i_clkevt_time_stop((void *)(uintptr_t)BASE_ADDR, 0);
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	allwinner_sun4i_clkevt_time_setup((void *)(uintptr_t)BASE_ADDR, 0, 25000 - TIMER_SYNC_TICKS); //cs->event_device->event_hz);
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	allwinner_sun4i_clkevt_time_start((void *)(uintptr_t)BASE_ADDR, 0, true);
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	allwinner_sun4i_show_regs();
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	return ENOERR;
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}
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static struct time_event_device allwinner_sun4i_timer_event_device  = {
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	.set_oneshot = allwinner_sun4i_timer_set_oneshot,
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	.set_periodic = allwinner_sun4i_timer_set_periodic,
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	.set_next_event = allwinner_sun4i_timer_set_next_event,
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	.name = "allwinner_sun4i_timer",
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	.irq_nr = IRQ_NUM
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};
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static int allwinner_sun4i_timer_init(struct clock_source *cs) {
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	uint32_t val;
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	REG32_STORE(BASE_ADDR + TIMER_INTVAL_REG(1), ~0);
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	REG32_STORE(BASE_ADDR + TIMER_CTL_REG(1),
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			TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
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			TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M));
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	REG32_STORE(BASE_ADDR + TIMER_CTL_REG(0),
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			TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M));
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	/* Make sure timer is stopped before playing with interrupts */
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	allwinner_sun4i_clkevt_time_stop((void *)(uintptr_t)BASE_ADDR, 0);
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	/* clear timer0 interrupt */
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	allwinner_sun4i_timer_clear_interrupt((void *)(uintptr_t)BASE_ADDR);
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	/* Enable timer0 interrupt */
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	val = REG32_LOAD(BASE_ADDR + TIMER_IRQ_EN_REG);
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	REG32_STORE(BASE_ADDR + TIMER_IRQ_EN_REG, val | TIMER_IRQ_EN(0));
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	allwinner_sun4i_show_regs();
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	return irq_attach(IRQ_NUM, allwinner_sun4i_timer_handler, 0, cs, "allwinner sun4i timer");
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}
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STATIC_IRQ_ATTACH(IRQ_NUM, allwinner_sun4i_timer_handler, &this_clock_source);
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PERIPH_MEMORY_DEFINE(allwinner_sun4i_timer, BASE_ADDR, 0x100);
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CLOCK_SOURCE_DEF(allwinner_sun4i_timer, allwinner_sun4i_timer_init, NULL,
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	&allwinner_sun4i_timer_event_device, NULL);
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