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/**
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 * @file
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 * @brief
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 *
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 * @author  Anton Kozlov
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 * @date    30.10.2014
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 */
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#include <bsp/stm32cube_hal.h>
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void SystemClock_Config(void) {
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	RCC_ClkInitTypeDef RCC_ClkInitStruct;
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	RCC_OscInitTypeDef RCC_OscInitStruct;
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	/* Enable Power Control clock */
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	__HAL_RCC_PWR_CLK_ENABLE();
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	/* The voltage scaling allows optimizing the power consumption when the device is
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     clocked below the maximum system frequency, to update the voltage scaling value
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     regarding system frequency refer to product datasheet.  */
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	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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	/* Enable HSE Oscillator and activate PLL with HSE as source */
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	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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	RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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	RCC_OscInitStruct.PLL.PLLM = 8;
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	RCC_OscInitStruct.PLL.PLLN = 336;
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	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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	RCC_OscInitStruct.PLL.PLLQ = 7;
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	HAL_RCC_OscConfig(&RCC_OscInitStruct);
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	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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     clocks dividers */
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	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
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	                               | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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#if OPTION_GET(BOOLEAN, errata_spi_wrong_last_bit)
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	/* One of possible workarounds, as suggested by
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	 * STM32F40x and STM32F41x Errata sheet is to decrease
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	 * APB clock speed. */
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	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV8;
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	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4;
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#else
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	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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#endif
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	HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
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	/* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported  */
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	if (HAL_GetREVID() == 0x1001) {
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		/* Enable the Flash prefetch */
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		__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
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	}
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}
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