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embox
/platform
/elvees
/eliot1
/arch
/
clkctr.c 
268 строк · 11.6 Кб
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/**
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 * @file
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 *
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 * @date Jan 24, 2023
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 * @author Anton Bondarev
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 */
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#include <stddef.h>
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#include <stdint.h>
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#include "eliot1_board.h"
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#include "hal_clkctr.h"
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#include "clkctr.h"
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/* ========================================================  PLLCFG  ========================================================= */
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#define CLKCTR_PLLCFG_SEL_Pos             (0UL)                     /*!< SEL (Bit 0)                                           */
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#define CLKCTR_PLLCFG_SEL_Msk             (0x1ffUL)                 /*!< SEL (Bitfield-Mask: 0x1ff)                            */
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#define CLKCTR_PLLCFG_MAN_Pos             (9UL)                     /*!< MAN (Bit 9)                                           */
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#define CLKCTR_PLLCFG_MAN_Msk             (0x200UL)                 /*!< MAN (Bitfield-Mask: 0x01)                             */
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#define CLKCTR_PLLCFG_OD_MAN_Pos          (10UL)                    /*!< OD_MAN (Bit 10)                                       */
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#define CLKCTR_PLLCFG_OD_MAN_Msk          (0x3c00UL)                /*!< OD_MAN (Bitfield-Mask: 0x0f)                          */
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#define CLKCTR_PLLCFG_NF_MAN_Pos          (14UL)                    /*!< NF_MAN (Bit 14)                                       */
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#define CLKCTR_PLLCFG_NF_MAN_Msk          (0x7ffc000UL)             /*!< NF_MAN (Bitfield-Mask: 0x1fff)                        */
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#define CLKCTR_PLLCFG_NR_MAN_Pos          (27UL)                    /*!< NR_MAN (Bit 27)                                       */
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#define CLKCTR_PLLCFG_NR_MAN_Msk          (0x78000000UL)            /*!< NR_MAN (Bitfield-Mask: 0x0f)                          */
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#define CLKCTR_PLLCFG_LOCK_Pos            (31UL)                    /*!< LOCK (Bit 31)                                         */
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#define CLKCTR_PLLCFG_LOCK_Msk            (0x80000000UL)            /*!< LOCK (Bitfield-Mask: 0x01)                            */
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/* ==========================================================  CFG  ========================================================== */
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#define CLKCTR_CFG_FCLK_SCALE_EN_Pos      (0UL)                     /*!< FCLK_SCALE_EN (Bit 0)                                 */
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#define CLKCTR_CFG_FCLK_SCALE_EN_Msk      (0x1UL)                   /*!< FCLK_SCALE_EN (Bitfield-Mask: 0x01)                   */
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#define CLKCTR_CFG_MAINCLK_SEL_Pos        (4UL)                     /*!< MAINCLK_SEL (Bit 4)                                   */
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#define CLKCTR_CFG_MAINCLK_SEL_Msk        (0x30UL)                  /*!< MAINCLK_SEL (Bitfield-Mask: 0x03)                     */
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#define CLKCTR_CFG_PLLREF_SEL_Pos         (6UL)                     /*!< PLLREF_SEL (Bit 6)                                    */
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#define CLKCTR_CFG_PLLREF_SEL_Msk         (0x40UL)                  /*!< PLLREF_SEL (Bitfield-Mask: 0x01)                      */
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#define CLKCTR_CFG_USBCLK_SEL_Pos         (7UL)                     /*!< USBCLK_SEL (Bit 7)                                    */
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#define CLKCTR_CFG_USBCLK_SEL_Msk         (0x80UL)                  /*!< USBCLK_SEL (Bitfield-Mask: 0x01)                      */
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#define CLKCTR_CFG_I2SCLK_SEL_Pos         (8UL)                     /*!< I2SCLK_SEL (Bit 8)                                    */
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#define CLKCTR_CFG_I2SCLK_SEL_Msk         (0x100UL)                 /*!< I2SCLK_SEL (Bitfield-Mask: 0x01)                      */
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#define CLKCTR_CFG_MCO_SEL_Pos            (9UL)                     /*!< MCO_SEL (Bit 9)                                       */
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#define CLKCTR_CFG_MCO_SEL_Msk            (0xe00UL)                 /*!< MCO_SEL (Bitfield-Mask: 0x07)                         */
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#define CLKCTR_CFG_MCO_EN_Pos             (13UL)                    /*!< MCO_EN (Bit 13)                                       */
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#define CLKCTR_CFG_MCO_EN_Msk             (0x2000UL)                /*!< MCO_EN (Bitfield-Mask: 0x01)                          */
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/* ========================================================  FCLKDIV  ======================================================== */
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#define CLKCTR_FCLKDIV_FCLKDIV_Pos        (0UL)                     /*!< FCLKDIV (Bit 0)                                       */
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#define CLKCTR_FCLKDIV_FCLKDIV_Msk        (0x1fUL)                  /*!< FCLKDIV (Bitfield-Mask: 0x1f)                         */
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#define CLKCTR_FCLKDIV_FCLKDIV_CUR_Pos    (16UL)                    /*!< FCLKDIV_CUR (Bit 16)                                  */
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#define CLKCTR_FCLKDIV_FCLKDIV_CUR_Msk    (0x1f0000UL)              /*!< FCLKDIV_CUR (Bitfield-Mask: 0x1f)                     */
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/* =======================================================  SYSCLKDIV  ======================================================= */
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#define CLKCTR_SYSCLKDIV_STSCLKDIV_Pos    (0UL)                     /*!< STSCLKDIV (Bit 0)                                     */
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#define CLKCTR_SYSCLKDIV_STSCLKDIV_Msk    (0x1fUL)                  /*!< STSCLKDIV (Bitfield-Mask: 0x1f)                       */
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#define CLKCTR_SYSCLKDIV_STSCLKDIV_CUR_Pos (16UL)                   /*!< STSCLKDIV_CUR (Bit 16)                                */
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#define CLKCTR_SYSCLKDIV_STSCLKDIV_CUR_Msk (0x1f0000UL)             /*!< STSCLKDIV_CUR (Bitfield-Mask: 0x1f)                   */
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/* ======================================================  QSPICLKDIV  ======================================================= */
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#define CLKCTR_QSPICLKDIV_QSPICLKDIV_Pos  (0UL)                     /*!< QSPICLKDIV (Bit 0)                                    */
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#define CLKCTR_QSPICLKDIV_QSPICLKDIV_Msk  (0x1fUL)                  /*!< QSPICLKDIV (Bitfield-Mask: 0x1f)                      */
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#define CLKCTR_QSPICLKDIV_QSPICLKDIV_CUR_Pos (16UL)                 /*!< QSPICLKDIV_CUR (Bit 16)                               */
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#define CLKCTR_QSPICLKDIV_QSPICLKDIV_CUR_Msk (0x1f0000UL)           /*!< QSPICLKDIV_CUR (Bitfield-Mask: 0x1f)                  */
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/* ======================================================  GNSSCLKDIV  ======================================================= */
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#define CLKCTR_GNSSCLKDIV_GNSSCLKDIV_Pos  (0UL)                     /*!< GNSSCLKDIV (Bit 0)                                    */
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#define CLKCTR_GNSSCLKDIV_GNSSCLKDIV_Msk  (0x7UL)                   /*!< GNSSCLKDIV (Bitfield-Mask: 0x07)                      */
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#define CLKCTR_GNSSCLKDIV_GNSSCLKDIV_CUR_Pos (16UL)                 /*!< GNSSCLKDIV_CUR (Bit 16)                               */
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#define CLKCTR_GNSSCLKDIV_GNSSCLKDIV_CUR_Msk (0x70000UL)            /*!< GNSSCLKDIV_CUR (Bitfield-Mask: 0x07)                  */
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#define CLKCTR_FORCE_CLK_DEV_EN 1
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#define CLKCTR_PLL_CFG_NR_MAN(x) \
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	(((x) << CLKCTR_PLLCFG_NR_MAN_Pos) & CLKCTR_PLLCFG_NR_MAN_Msk)
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#define CLKCTR_PLL_CFG_NF_MAN(x) \
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	(((x) << CLKCTR_PLLCFG_NF_MAN_Pos) & CLKCTR_PLLCFG_NF_MAN_Msk)
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#define CLKCTR_PLL_CFG_OD_MAN(x) \
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	(((x) << CLKCTR_PLLCFG_OD_MAN_Pos) & CLKCTR_PLLCFG_OD_MAN_Msk)
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#define CLKCTR_PLL_CFG_MAN(x) \
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	(((x)<< CLKCTR_PLLCFG_MAN_Pos) & CLKCTR_PLLCFG_MAN_Msk)
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#define CLKCTR_PLL_CFG_SEL(x) \
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	(((x) << CLKCTR_PLLCFG_SEL_Pos) & CLKCTR_PLLCFG_SEL_Msk)
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static uint32_t MAINCLK_FREQUENCY = BOARD_HFI_FREQUENCY;
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int clkctr_get_pll_config(struct clkctr_regs *base,
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		struct clkctr_pll_cfg *config) {
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	uint32_t reg = base->PLLCFG;
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	config->lock = (reg & CLKCTR_PLLCFG_LOCK_Msk) >> CLKCTR_PLLCFG_LOCK_Pos;
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	config->nr_man = (reg & CLKCTR_PLLCFG_NR_MAN_Msk)
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			>> CLKCTR_PLLCFG_NR_MAN_Pos;
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	config->nf_man = (reg & CLKCTR_PLLCFG_NF_MAN_Msk)
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			>> CLKCTR_PLLCFG_NF_MAN_Pos;
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	config->od_man = (reg & CLKCTR_PLLCFG_OD_MAN_Msk)
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			>> CLKCTR_PLLCFG_OD_MAN_Pos;
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	config->man = (reg & CLKCTR_PLLCFG_MAN_Msk) >> CLKCTR_PLLCFG_MAN_Pos;
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	config->sel = (reg & CLKCTR_PLLCFG_SEL_Msk) >> CLKCTR_PLLCFG_SEL_Pos;
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	return 0;
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}
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int clkctr_set_pll_config(struct clkctr_regs *base,
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		struct clkctr_pll_cfg config) {
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	uint32_t pll_cfg = CLKCTR_PLL_CFG_NR_MAN(
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			config.nr_man) | CLKCTR_PLL_CFG_NF_MAN(config.nr_man)
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			| CLKCTR_PLL_CFG_OD_MAN(config.od_man)
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			| CLKCTR_PLL_CFG_MAN(config.man)
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			| CLKCTR_PLL_CFG_SEL(config.sel);
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	if (config.sel != 0) {
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		/* stop PLL. */
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		base->PLLCFG = 0;
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		/* start PLL. */
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		base->PLLCFG = pll_cfg;
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		while ((base->PLLCFG & CLKCTR_PLLCFG_LOCK_Msk) == 0) {
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			;
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		}
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	} else {
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		base->PLLCFG = pll_cfg;
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	}
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	return 0;
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}
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int clkctr_set_switch_main_clk(struct clkctr_regs *base, uint32_t value) {
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	uint32_t cfgReg = base->CFG;
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	cfgReg &= ~CLKCTR_CFG_MAINCLK_SEL_Msk;
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	cfgReg |= (value << CLKCTR_CFG_MAINCLK_SEL_Pos);
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	base->CFG = cfgReg;
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	return 0;
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}
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int clkctr_set_switch_pll_ref(struct clkctr_regs *base, uint32_t value) {
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	uint32_t cfgReg = base->CFG;
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	cfgReg &= ~(CLKCTR_CFG_PLLREF_SEL_Msk);
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	cfgReg |= (value << CLKCTR_CFG_PLLREF_SEL_Pos);
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	base->CFG = cfgReg;
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	return 0;
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}
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void clkctr_set_pll(struct clkctr_regs *base, uint32_t xti_hz, uint16_t pll_mul) {
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	struct clkctr_pll_cfg config;
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	clkctr_set_switch_main_clk(base, CLKCTR_CLK_TYPE_HFI);
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	clkctr_get_pll_config(base, &config);
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	config.sel = 0;
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	clkctr_set_pll_config(base, config);
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	/* PLLCLK (HFI or XTI). */
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	if (xti_hz == 0) {
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		clkctr_set_switch_pll_ref(base, CLKCTR_CLK_TYPE_HFI);
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		MAINCLK_FREQUENCY = BOARD_HFI_FREQUENCY;
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	} else {
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		clkctr_set_switch_pll_ref(base, CLKCTR_CLK_TYPE_XTI);
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		MAINCLK_FREQUENCY = xti_hz;
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	}
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	if (pll_mul > PLL_MAX_MULTIPLIER) {
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		pll_mul = PLL_MAX_MULTIPLIER;
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	}
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	if ((MAINCLK_FREQUENCY * (pll_mul + 1)) > CLKCTR_PLLCLK_MAX) {
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		pll_mul = (CLKCTR_PLLCLK_MAX / MAINCLK_FREQUENCY) - 1;
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	}
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	if ((MAINCLK_FREQUENCY * (pll_mul + 1)) < CLKCTR_PLLCLK_OD_MIN) {
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		pll_mul = PLL_MIN_MULTIPLIER;
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	}
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	if (pll_mul > PLL_MIN_MULTIPLIER) {
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		clkctr_get_pll_config(base, &config);
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		config.man = 0;
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		config.sel = pll_mul;
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		clkctr_set_pll_config(base, config);
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		clkctr_set_switch_main_clk(base, CLKCTR_CLK_TYPE_PLL);
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		MAINCLK_FREQUENCY = MAINCLK_FREQUENCY * (pll_mul + 1);
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	}
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}
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uint32_t clk_get_sys_clk_div(struct clkctr_regs *base) {
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	return ((base->SYSCLKDIV & CLKCTR_SYSCLKDIV_STSCLKDIV_Msk)
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			>> CLKCTR_SYSCLKDIV_STSCLKDIV_Pos) + 1;
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}
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uint32_t clkctr_set_sys_clk_div(struct clkctr_regs *base, uint32_t value) {
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	base->SYSCLKDIV = ((value - 1) << CLKCTR_SYSCLKDIV_STSCLKDIV_Pos)
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			& CLKCTR_SYSCLKDIV_STSCLKDIV_Msk;
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	while (clk_get_sys_clk_div(base) != value)
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		;
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	return value;
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}
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uint32_t clkctr_get_fclk_div(struct clkctr_regs *base) {
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	return ((base->FCLKDIV & CLKCTR_FCLKDIV_FCLKDIV_Msk)
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			>> CLKCTR_FCLKDIV_FCLKDIV_Pos) + 1;
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}
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uint32_t clkctr_set_fclk_div(struct clkctr_regs *base, uint32_t value) {
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	base->FCLKDIV = ((value - 1) << CLKCTR_FCLKDIV_FCLKDIV_Pos)
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			& CLKCTR_FCLKDIV_FCLKDIV_Msk;
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	while (clkctr_get_fclk_div(base) != value) {
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		;
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	}
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	return value;
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}
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uint32_t clkctr_get_qspi_clk_div(struct clkctr_regs *base) {
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	return ((base->QSPICLKDIV & CLKCTR_QSPICLKDIV_QSPICLKDIV_Msk)
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			>> CLKCTR_QSPICLKDIV_QSPICLKDIV_Pos) + 1;
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}
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uint32_t clkctr_set_qspi_clk_div(struct clkctr_regs *base, uint32_t value) {
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	base->QSPICLKDIV = ((value - 1) << CLKCTR_QSPICLKDIV_QSPICLKDIV_Pos)
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			& CLKCTR_QSPICLKDIV_QSPICLKDIV_Msk;
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	while (clkctr_get_qspi_clk_div(base) != value) {
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		;
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	}
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	return value;
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}
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uint32_t clkctr_set_gnss_clk_div(struct clkctr_regs *base, uint32_t value) {
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	base->GNSSCLKDIV = ((value - 1) << CLKCTR_GNSSCLKDIV_GNSSCLKDIV_Pos)
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			& CLKCTR_GNSSCLKDIV_GNSSCLKDIV_Msk;
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#ifdef CLKCTR_NO_GNNS_BUG_ELIOT1RTL_2
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    while (CLKCTR_GetGNSSClkDiv(base) != value)
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        ;
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#endif
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	return value;
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}
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void clkctr_set_sys_div(struct clkctr_regs *base, uint16_t fclk_div,
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		uint16_t sysclk_div, uint16_t gnssclk_div, uint16_t qspiclk_div) {
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	if (sysclk_div > CLKCTR_MAX_SYSCLK_DIV) {
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		sysclk_div = CLKCTR_MAX_SYSCLK_DIV;
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	}
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	clkctr_set_sys_clk_div(base, sysclk_div + 1);
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	if (fclk_div > CLKCTR_MAX_FCLK_DIV) {
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		fclk_div = CLKCTR_MAX_FCLK_DIV;
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	}
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	clkctr_set_fclk_div(base, fclk_div + 1);
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	if (gnssclk_div > CLKCTR_MAX_GNSSCLK_DIV) {
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		gnssclk_div = CLKCTR_MAX_GNSSCLK_DIV;
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	}
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	clkctr_set_gnss_clk_div(base, gnssclk_div + 1);
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	if (qspiclk_div > CLKCTR_MAX_QSPICLK_DIV) {
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		qspiclk_div = CLKCTR_MAX_QSPICLK_DIV;
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	}
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	clkctr_set_qspi_clk_div(base, qspiclk_div + 1);
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}
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