embox

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/**
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 * @file
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 * @brief
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 *
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 * @date 10.05.2020
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 * @author Alexander Kalmuk
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 */
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#include <assert.h>
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#include <hw_cache.h>
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#include <hw_otpc.h>
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#include <hw_rtc.h>
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#include <hw_sys.h>
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#include <hw_watchdog.h>
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#include <string.h>
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#include <sys_clock_mgr.h>
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#include <sys_power_mgr.h>
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#include <time.h>
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#include <arm/fpu.h>
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#include <framework/mod/options.h>
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#include <hal/cpu_idle.h>
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#include <hal/clock.h>
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#include <hal/reg.h>
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#include <kernel/irq.h>
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#include <kernel/time/clock_source.h>
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#include <kernel/time/time.h>
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#include <util/log.h>
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#include <config/custom_config_qspi.h>
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extern const struct clock_source *cs_jiffies;
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static void switch_jiffies_to(int freq) {
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	struct clock_source *cs = (struct clock_source *)cs_jiffies;
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	struct time_counter_device *cd = cs->counter_device;
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	cd->cycle_hz = freq;
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	clock_source_set_periodic(cs, clock_freq());
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}
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void clk_update_hook(void) {
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	static uint16_t cur_clk = 1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos;
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	uint16_t clk;
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#define FREQ_MASK                                            \
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	((1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos)       \
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	    | (1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos)   \
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	    | (1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos) \
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	    | (1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos))
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	clk = CRG_TOP->CLK_CTRL_REG & FREQ_MASK;
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	switch (clk) {
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	case (1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos):
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		if (cur_clk != clk) {
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			switch_jiffies_to(32000000);
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		}
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		break;
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	case (1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos):
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		if (cur_clk != clk) {
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			switch_jiffies_to(96000000);
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		}
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		break;
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	case (1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos):
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	case (1 << CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos):
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	default:
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		break;
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	}
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	cur_clk = clk;
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#undef FREQ_MASK
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}
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extern int deepsleep_enter(void);
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static uint32_t arch_deepsleep_flags = 0;
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void arch_deepsleep_disable(uint32_t mask) {
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	ipl_t ipl;
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	ipl = ipl_save();
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	arch_deepsleep_flags |= mask;
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	ipl_restore(ipl);
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}
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void arch_deepsleep_enable(uint32_t mask) {
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	ipl_t ipl;
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	ipl = ipl_save();
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	{ arch_deepsleep_flags &= ~mask; }
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	ipl_restore(ipl);
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}
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static uint32_t arch_deepsleep_start(ipl_t *ipl) {
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	*ipl = ipl_save();
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	return arch_deepsleep_flags;
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}
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static void arch_deepsleep_finish(ipl_t ipl) {
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	ipl_restore(ipl);
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}
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void arch_cpu_idle(void) {
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	ipl_t ipl;
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	clk_update_hook();
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	if (arch_deepsleep_start(&ipl)) {
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		__asm__ __volatile__("wfi");
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	}
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	else {
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		deepsleep_enter();
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	}
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	arch_deepsleep_finish(ipl);
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}
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