qemu

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/*
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 * Host specific cpu identification for RISC-V.
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 */
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#include "qemu/osdep.h"
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#include "host/cpuinfo.h"
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#ifdef CONFIG_ASM_HWPROBE_H
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#include <asm/hwprobe.h>
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#include <sys/syscall.h>
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#endif
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unsigned cpuinfo;
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static volatile sig_atomic_t got_sigill;
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static void sigill_handler(int signo, siginfo_t *si, void *data)
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{
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    /* Skip the faulty instruction */
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    ucontext_t *uc = (ucontext_t *)data;
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#ifdef __linux__
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    uc->uc_mcontext.__gregs[REG_PC] += 4;
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#elif defined(__OpenBSD__)
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    uc->sc_sepc += 4;
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#else
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# error Unsupported OS
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#endif
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    got_sigill = 1;
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}
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/* Called both as constructor and (possibly) via other constructors. */
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unsigned __attribute__((constructor)) cpuinfo_init(void)
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{
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    unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND;
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    unsigned info = cpuinfo;
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    if (info) {
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        return info;
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    }
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    /* Test for compile-time settings. */
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#if defined(__riscv_arch_test) && defined(__riscv_zba)
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    info |= CPUINFO_ZBA;
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#endif
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#if defined(__riscv_arch_test) && defined(__riscv_zbb)
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    info |= CPUINFO_ZBB;
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#endif
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#if defined(__riscv_arch_test) && defined(__riscv_zicond)
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    info |= CPUINFO_ZICOND;
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#endif
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    left &= ~info;
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#ifdef CONFIG_ASM_HWPROBE_H
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    if (left) {
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        /*
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         * TODO: glibc 2.40 will introduce <sys/hwprobe.h>, which
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         * provides __riscv_hwprobe and __riscv_hwprobe_one,
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         * which is a slightly cleaner interface.
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         */
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        struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_IMA_EXT_0 };
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        if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0
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            && pair.key >= 0) {
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            info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0;
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            info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0;
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            left &= ~(CPUINFO_ZBA | CPUINFO_ZBB);
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#ifdef RISCV_HWPROBE_EXT_ZICOND
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            info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0;
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            left &= ~CPUINFO_ZICOND;
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#endif
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        }
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    }
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#endif /* CONFIG_ASM_HWPROBE_H */
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    if (left) {
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        struct sigaction sa_old, sa_new;
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        memset(&sa_new, 0, sizeof(sa_new));
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        sa_new.sa_flags = SA_SIGINFO;
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        sa_new.sa_sigaction = sigill_handler;
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        sigaction(SIGILL, &sa_new, &sa_old);
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        if (left & CPUINFO_ZBA) {
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            /* Probe for Zba: add.uw zero,zero,zero. */
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            got_sigill = 0;
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            asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero"
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                         : : : "memory");
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            info |= got_sigill ? 0 : CPUINFO_ZBA;
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            left &= ~CPUINFO_ZBA;
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        }
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        if (left & CPUINFO_ZBB) {
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            /* Probe for Zbb: andn zero,zero,zero. */
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            got_sigill = 0;
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            asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero"
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                         : : : "memory");
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            info |= got_sigill ? 0 : CPUINFO_ZBB;
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            left &= ~CPUINFO_ZBB;
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        }
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        if (left & CPUINFO_ZICOND) {
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            /* Probe for Zicond: czero.eqz zero,zero,zero. */
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            got_sigill = 0;
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            asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero"
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                         : : : "memory");
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            info |= got_sigill ? 0 : CPUINFO_ZICOND;
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            left &= ~CPUINFO_ZICOND;
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        }
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        sigaction(SIGILL, &sa_old, NULL);
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        assert(left == 0);
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    }
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    info |= CPUINFO_ALWAYS;
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    cpuinfo = info;
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    return info;
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}
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